From: Florian Fainelli <f.fainelli@gmail.com>
To: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>,
Sean Wang <sean.wang@mediatek.com>,
Landen Chao <Landen.Chao@mediatek.com>,
Andrew Lunn <andrew@lunn.ch>,
Vivien Didelot <vivien.didelot@gmail.com>,
Vladimir Oltean <olteanv@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Russell King <linux@armlinux.org.uk>,
netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH net] net: dsa: mt7530: setup core clock even in TRGMII mode
Date: Wed, 10 Mar 2021 19:21:17 -0800 [thread overview]
Message-ID: <79be95b7-0c56-f831-2f3f-5a41006d0037@gmail.com> (raw)
In-Reply-To: <20210311012108.7190-1-ilya.lipnitskiy@gmail.com>
On 3/10/2021 5:21 PM, Ilya Lipnitskiy wrote:
> A recent change to MIPS ralink reset logic made it so mt7530 actually
> resets the switch on platforms such as mt7621 (where bit 2 is the reset
> line for the switch). That exposed an issue where the switch would not
> function properly in TRGMII mode after a reset.
>
> Reconfigure core clock in TRGMII mode to fix the issue.
>
> Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled.
>
> Fixes: 3f9ef7785a9c ("MIPS: ralink: manage low reset lines")
> Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
--
Florian
next prev parent reply other threads:[~2021-03-11 3:22 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-11 1:21 Ilya Lipnitskiy
2021-03-11 3:21 ` Florian Fainelli [this message]
2021-03-12 8:07 ` [PATCH net,v2] " Ilya Lipnitskiy
2021-03-19 10:25 ` René van Dorst
2021-03-19 12:47 ` Aw: " Frank Wunderlich
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