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Wed, 17 Dec 2025 15:24:49 -0800 From: Nicolin Chen To: CC: , , , , , , , , , , , Subject: [PATCH v8 5/7] iommu/arm-smmu-v3: Populate smmu_domain->invs when attaching masters Date: Wed, 17 Dec 2025 15:24:30 -0800 Message-ID: <79cd18a1a959ee2e54683e8c465b799d49ec48b5.1766013662.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E61:EE_|CY3PR12MB9656:EE_ X-MS-Office365-Filtering-Correlation-Id: 53a4027f-7140-4caf-cc4f-08de3dc38234 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?zaVtgJkhWZMvS54pHma1DZw+sh194RJE1JUEre5Uq4VrkGOv5x1CqZOI1mnx?= =?us-ascii?Q?BcjJIDOVmXaKmVq5HixxfVRVfJ2qBapCdIhjO2fmFXEjyqh2UC8sBfzZN0b8?= =?us-ascii?Q?HcsRGvqIS9xzQSfcG+1/euACcPy7NKKgAZonvYKmypxqpjX+XbTWRdp1JTY+?= =?us-ascii?Q?GlqbM9Or6olT6LQlxU+Atti+/XoRDNToy0GW8/B6Snmib9CysCJCp+6O9EsM?= =?us-ascii?Q?gfmwQCowbo6aoKCZJmjDDsUOexY+oyNWUgxut11no0RMD5pHScy+UySBZQLG?= =?us-ascii?Q?q/uXkZZVRq9yospmIOQDJpDpeMc2uuU4ADqU5/yuInyKkTAZDYaGwatyr+MU?= =?us-ascii?Q?+Kbv81Ib58XnRhXlzCmg2aqob1sryXN3FMfpm9kNXuyn9bPCv5aBZ0KnvLQm?= =?us-ascii?Q?qWy2Kdt7+YqNjLfR39FKi+e/5h7Vt4n5iMGnGrla7b6MSFlTYzisyOGXBc9c?= =?us-ascii?Q?/6UDyy068FXldnDaTcdeg29hZqnu3BYhYdmTTk0XbYdT9Rts5sY9gwYCEi3e?= =?us-ascii?Q?1cR9LTpyJiBMRAcMRjfr1xuw5ToU599KoyLsPw4TbI5Xy8OidEXnOgjmVlIN?= =?us-ascii?Q?TwEnX69gy9lr93ssPcO6nk9hj2usBLCF55QmLpJF1AUTymOQCoB6PlBjmbtO?= =?us-ascii?Q?5gNaIsfgVJ4v9ZotnCYH40symeAhWbaIFeKH98ejuiIff98U9gBoa4H1Lt4d?= =?us-ascii?Q?DrUhlQcvvL3HtUmdoVuCS+/jGllreWLS4WAIwZBMJd43ZEXXqCmZLd2dpx8Q?= =?us-ascii?Q?FsFZYwXQ+S/a/uzYTac5AsR4Yi8SGAdH33aceSkloTE/lPy5xRUa16rjU06p?= =?us-ascii?Q?plCUgoOfI4LOoe/f52v/djxUD4yCXnTT5ZF6E/v0O6aUOSPBbsNbzEE88LGY?= =?us-ascii?Q?aiCtqtUDcel0Maeue32HwwVW+KuV41nRB4qBi9soyw1DOh7MuH16o8luQHK7?= =?us-ascii?Q?SzfFH5ZEciu19d2aNFgXD4PKlb6NCs4/n+jEpUM23kGBnIR+UM3BCvCeH6iF?= =?us-ascii?Q?eo3d2eKjneI4purUWh7YcXVvCseTNOXI4zaRUMltWfMqzgRzPW71Q2d49BTj?= =?us-ascii?Q?e6xmYlgs/OpuoNTUx8bgGyMO0sKM+Dhu6jkt9hicdSlnKMY878yb27l0w1vs?= =?us-ascii?Q?kAAjx0qO7nXaiJYxPS4HXUsMHosIqVjW9Jx2CxRZyMx7AFzXuBrs0pEiQbnL?= =?us-ascii?Q?N2cP/14KSRCPdF+3zb6Fs37pF6IaiUxHzLxS59kOM3+aP4ms6bmC/xW6HAXA?= =?us-ascii?Q?5E2juW9nX9MRFfqhBhhPRplUUh4uZum3kiD5UGn6D4RsIUfXAYTfqsoTMrwS?= =?us-ascii?Q?QufP0udlxFy6Pf5jGPPyDE9TonOWWd8HlVfqqgS8LvWVh1qyigr9fX+Rflmo?= =?us-ascii?Q?iW7n+APox1tyrm8vgsz6/nIGANVwKNDyN3cDMfEOS1psVv23gYlfTCGN+F6p?= =?us-ascii?Q?/lw8/K/yFND75Ynqt7Kc2AehCILpMRYUXOt9WOisrDrETezKKHjTFzGGgRWo?= =?us-ascii?Q?MpEOZVLzOU82WNojV1lQlTL0H0DmNEnIxgm4zaG855lkGklV/g3+DuMWlprp?= =?us-ascii?Q?he9YEAG4cBBqZEWjRWc=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Dec 2025 23:25:04.3703 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 53a4027f-7140-4caf-cc4f-08de3dc38234 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E61.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9656 Update the invs array with the invalidations required by each domain type during attachment operations. Only an SVA domain or a paging domain will have an invs array: a. SVA domain will add an INV_TYPE_S1_ASID per SMMU and an INV_TYPE_ATS per SID b. Non-nesting-parent paging domain with no ATS-enabled master will add a single INV_TYPE_S1_ASID or INV_TYPE_S2_VMID per SMMU c. Non-nesting-parent paging domain with ATS-enabled master(s) will do (b) and add an INV_TYPE_ATS per SID d. Nesting-parent paging domain will add an INV_TYPE_S2_VMID followed by an INV_TYPE_S2_VMID_S1_CLEAR per vSMMU. For an ATS-enabled master, it will add an INV_TYPE_ATS_FULL per SID Note that case #d prepares for a future implementation of VMID allocation which requires a followup series for S2 domain sharing. So when a nesting parent domain is attached through a vSMMU instance using a nested domain. VMID will be allocated per vSMMU instance v.s. currectly per S2 domain. The per-domain invalidation is not needed until the domain is attached to a master (when it starts to possibly use TLB). This will make it possible to attach the domain to multiple SMMUs and avoid unnecessary invalidation overhead during teardown if no STEs/CDs refer to the domain. It also means that when the last device is detached, the old domain must flush its ASID or VMID, since any new iommu_unmap() call would not trigger invalidations given an empty domain->invs array. Introduce some arm_smmu_invs helper functions for building scratch arrays, preparing and installing old/new domain's invalidation arrays. Co-developed-by: Jason Gunthorpe Signed-off-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 17 ++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 253 +++++++++++++++++++- 2 files changed, 269 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index f98774962012..f8dc96476c43 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1101,6 +1101,21 @@ static inline bool arm_smmu_master_canwbs(struct arm_smmu_master *master) IOMMU_FWSPEC_PCI_RC_CANWBS; } +/** + * struct arm_smmu_inv_state - Per-domain invalidation array state + * @invs_ptr: points to the domain->invs (unwinding nesting/etc.) or is NULL if + * no change should be made + * @old_invs: the original invs array + * @new_invs: for new domain, this is the new invs array to update domain->invs; + * for old domain, this is the master->build_invs to pass in as the + * to_unref argument to an arm_smmu_invs_unref() call + */ +struct arm_smmu_inv_state { + struct arm_smmu_invs __rcu **invs_ptr; + struct arm_smmu_invs *old_invs; + struct arm_smmu_invs *new_invs; +}; + struct arm_smmu_attach_state { /* Inputs */ struct iommu_domain *old_domain; @@ -1110,6 +1125,8 @@ struct arm_smmu_attach_state { ioasid_t ssid; /* Resulting state */ struct arm_smmu_vmaster *vmaster; + struct arm_smmu_inv_state old_domain_invst; + struct arm_smmu_inv_state new_domain_invst; bool ats_enabled; }; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index cc85e7a10ea8..9a2281b5d9da 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3068,6 +3068,116 @@ static void arm_smmu_disable_iopf(struct arm_smmu_master *master, iopf_queue_remove_device(master->smmu->evtq.iopf, master->dev); } +static struct arm_smmu_inv * +arm_smmu_master_build_inv(struct arm_smmu_master *master, + enum arm_smmu_inv_type type, u32 id, ioasid_t ssid, + size_t pgsize) +{ + struct arm_smmu_invs *build_invs = master->build_invs; + struct arm_smmu_inv *cur, inv = { + .smmu = master->smmu, + .type = type, + .id = id, + .pgsize = pgsize, + }; + + if (WARN_ON(build_invs->num_invs >= build_invs->max_invs)) + return NULL; + cur = &build_invs->inv[build_invs->num_invs]; + build_invs->num_invs++; + + *cur = inv; + switch (type) { + case INV_TYPE_S1_ASID: + if (master->smmu->features & ARM_SMMU_FEAT_E2H) { + cur->size_opcode = CMDQ_OP_TLBI_EL2_VA; + cur->nsize_opcode = CMDQ_OP_TLBI_EL2_ASID; + } else { + cur->size_opcode = CMDQ_OP_TLBI_NH_VA; + cur->nsize_opcode = CMDQ_OP_TLBI_NH_ASID; + } + break; + case INV_TYPE_S2_VMID: + cur->size_opcode = CMDQ_OP_TLBI_S2_IPA; + cur->nsize_opcode = CMDQ_OP_TLBI_S12_VMALL; + break; + case INV_TYPE_S2_VMID_S1_CLEAR: + cur->size_opcode = cur->nsize_opcode = CMDQ_OP_TLBI_NH_ALL; + break; + case INV_TYPE_ATS: + case INV_TYPE_ATS_FULL: + cur->size_opcode = cur->nsize_opcode = CMDQ_OP_ATC_INV; + break; + } + + return cur; +} + +/* + * Use the preallocated scratch array at master->build_invs, to build a to_merge + * or to_unref array, to pass into a following arm_smmu_invs_merge/unref() call. + * + * Do not free the returned invs array. It is reused, and will be overwritten by + * the next arm_smmu_master_build_invs() call. + */ +static struct arm_smmu_invs * +arm_smmu_master_build_invs(struct arm_smmu_master *master, bool ats_enabled, + ioasid_t ssid, struct arm_smmu_domain *smmu_domain) +{ + const bool nesting = smmu_domain->nest_parent; + size_t pgsize = 0, i; + + iommu_group_mutex_assert(master->dev); + + master->build_invs->num_invs = 0; + + /* Range-based invalidation requires the leaf pgsize for calculation */ + if (master->smmu->features & ARM_SMMU_FEAT_RANGE_INV) + pgsize = __ffs(smmu_domain->domain.pgsize_bitmap); + + switch (smmu_domain->stage) { + case ARM_SMMU_DOMAIN_SVA: + case ARM_SMMU_DOMAIN_S1: + if (!arm_smmu_master_build_inv(master, INV_TYPE_S1_ASID, + smmu_domain->cd.asid, + IOMMU_NO_PASID, pgsize)) + return NULL; + break; + case ARM_SMMU_DOMAIN_S2: + if (!arm_smmu_master_build_inv(master, INV_TYPE_S2_VMID, + smmu_domain->s2_cfg.vmid, + IOMMU_NO_PASID, pgsize)) + return NULL; + break; + default: + WARN_ON(true); + return NULL; + } + + /* All the nested S1 ASIDs have to be flushed when S2 parent changes */ + if (nesting) { + if (!arm_smmu_master_build_inv( + master, INV_TYPE_S2_VMID_S1_CLEAR, + smmu_domain->s2_cfg.vmid, IOMMU_NO_PASID, 0)) + return NULL; + } + + for (i = 0; ats_enabled && i < master->num_streams; i++) { + /* + * If an S2 used as a nesting parent is changed we have no + * option but to completely flush the ATC. + */ + if (!arm_smmu_master_build_inv( + master, nesting ? INV_TYPE_ATS_FULL : INV_TYPE_ATS, + master->streams[i].id, ssid, 0)) + return NULL; + } + + /* Note this build_invs must have been sorted */ + + return master->build_invs; +} + static void arm_smmu_remove_master_domain(struct arm_smmu_master *master, struct iommu_domain *domain, ioasid_t ssid) @@ -3097,6 +3207,131 @@ static void arm_smmu_remove_master_domain(struct arm_smmu_master *master, kfree(master_domain); } +/* + * During attachment, the updates of the two domain->invs arrays are sequenced: + * 1. new domain updates its invs array, merging master->build_invs + * 2. new domain starts to include the master during its invalidation + * 3. master updates its STE switching from the old domain to the new domain + * 4. old domain still includes the master during its invalidation + * 5. old domain updates its invs array, unreferencing master->build_invs + * + * For 1 and 5, prepare the two updated arrays in advance, handling any changes + * that can possibly failure. So the actual update of either 1 or 5 won't fail. + * arm_smmu_asid_lock ensures that the old invs in the domains are intact while + * we are sequencing to update them. + */ +static int arm_smmu_attach_prepare_invs(struct arm_smmu_attach_state *state, + struct arm_smmu_domain *new_smmu_domain) +{ + struct arm_smmu_domain *old_smmu_domain = + to_smmu_domain_devices(state->old_domain); + struct arm_smmu_master *master = state->master; + ioasid_t ssid = state->ssid; + + /* + * At this point a NULL domain indicates the domain doesn't use the + * IOTLB, see to_smmu_domain_devices(). + */ + if (new_smmu_domain) { + struct arm_smmu_inv_state *invst = &state->new_domain_invst; + struct arm_smmu_invs *build_invs; + + invst->invs_ptr = &new_smmu_domain->invs; + invst->old_invs = rcu_dereference_protected( + new_smmu_domain->invs, + lockdep_is_held(&arm_smmu_asid_lock)); + build_invs = arm_smmu_master_build_invs( + master, state->ats_enabled, ssid, new_smmu_domain); + if (!build_invs) + return -EINVAL; + + invst->new_invs = + arm_smmu_invs_merge(invst->old_invs, build_invs); + if (IS_ERR(invst->new_invs)) + return PTR_ERR(invst->new_invs); + } + + if (old_smmu_domain) { + struct arm_smmu_inv_state *invst = &state->old_domain_invst; + + invst->invs_ptr = &old_smmu_domain->invs; + /* A re-attach case might have a different ats_enabled state */ + if (new_smmu_domain == old_smmu_domain) + invst->old_invs = state->new_domain_invst.new_invs; + else + invst->old_invs = rcu_dereference_protected( + old_smmu_domain->invs, + lockdep_is_held(&arm_smmu_asid_lock)); + /* For old_smmu_domain, new_invs points to master->build_invs */ + invst->new_invs = arm_smmu_master_build_invs( + master, master->ats_enabled, ssid, old_smmu_domain); + } + + return 0; +} + +/* Must be installed before arm_smmu_install_ste_for_dev() */ +static void +arm_smmu_install_new_domain_invs(struct arm_smmu_attach_state *state) +{ + struct arm_smmu_inv_state *invst = &state->new_domain_invst; + + if (!invst->invs_ptr) + return; + + rcu_assign_pointer(*invst->invs_ptr, invst->new_invs); + kfree_rcu(invst->old_invs, rcu); +} + +/* + * When an array entry's users count reaches zero, it means the ASID/VMID is no + * longer being invalidated by map/unmap and must be cleaned. The rule is that + * all ASIDs/VMIDs not in an invalidation array are left cleared in the IOTLB. + */ +static void arm_smmu_inv_flush_iotlb_tag(struct arm_smmu_inv *inv) +{ + struct arm_smmu_cmdq_ent cmd = {}; + + switch (inv->type) { + case INV_TYPE_S1_ASID: + cmd.tlbi.asid = inv->id; + break; + case INV_TYPE_S2_VMID: + /* S2_VMID using nsize_opcode covers S2_VMID_S1_CLEAR */ + cmd.tlbi.vmid = inv->id; + break; + default: + return; + } + + cmd.opcode = inv->nsize_opcode; + arm_smmu_cmdq_issue_cmd_with_sync(inv->smmu, &cmd); +} + +/* Should be installed after arm_smmu_install_ste_for_dev() */ +static void +arm_smmu_install_old_domain_invs(struct arm_smmu_attach_state *state) +{ + struct arm_smmu_inv_state *invst = &state->old_domain_invst; + struct arm_smmu_invs *old_invs = invst->old_invs; + struct arm_smmu_invs *new_invs; + + lockdep_assert_held(&arm_smmu_asid_lock); + + if (!invst->invs_ptr) + return; + + arm_smmu_invs_unref(old_invs, invst->new_invs, + arm_smmu_inv_flush_iotlb_tag); + + new_invs = arm_smmu_invs_purge(old_invs); + if (!new_invs) + return; + + rcu_assign_pointer(*invst->invs_ptr, new_invs); + kfree_rcu(old_invs, rcu); +} + /* * Start the sequence to attach a domain to a master. The sequence contains three * steps: @@ -3154,12 +3389,16 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, arm_smmu_ats_supported(master); } + ret = arm_smmu_attach_prepare_invs(state, smmu_domain); + if (ret) + return ret; + if (smmu_domain) { if (new_domain->type == IOMMU_DOMAIN_NESTED) { ret = arm_smmu_attach_prepare_vmaster( state, to_smmu_nested_domain(new_domain)); if (ret) - return ret; + goto err_unprepare_invs; } master_domain = kzalloc(sizeof(*master_domain), GFP_KERNEL); @@ -3207,6 +3446,8 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, atomic_inc(&smmu_domain->nr_ats_masters); list_add(&master_domain->devices_elm, &smmu_domain->devices); spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); + + arm_smmu_install_new_domain_invs(state); } if (!state->ats_enabled && master->ats_enabled) { @@ -3226,6 +3467,8 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, kfree(master_domain); err_free_vmaster: kfree(state->vmaster); +err_unprepare_invs: + kfree(state->new_domain_invst.new_invs); return ret; } @@ -3257,6 +3500,7 @@ void arm_smmu_attach_commit(struct arm_smmu_attach_state *state) } arm_smmu_remove_master_domain(master, state->old_domain, state->ssid); + arm_smmu_install_old_domain_invs(state); master->ats_enabled = state->ats_enabled; } @@ -3438,12 +3682,19 @@ static int arm_smmu_blocking_set_dev_pasid(struct iommu_domain *new_domain, { struct arm_smmu_domain *smmu_domain = to_smmu_domain(old_domain); struct arm_smmu_master *master = dev_iommu_priv_get(dev); + struct arm_smmu_attach_state state = { + .master = master, + .old_domain = old_domain, + .ssid = pasid, + }; mutex_lock(&arm_smmu_asid_lock); + arm_smmu_attach_prepare_invs(&state, NULL); arm_smmu_clear_cd(master, pasid); if (master->ats_enabled) arm_smmu_atc_inv_master(master, pasid); arm_smmu_remove_master_domain(master, &smmu_domain->domain, pasid); + arm_smmu_install_old_domain_invs(&state); mutex_unlock(&arm_smmu_asid_lock); /* -- 2.43.0