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[78.26.46.173]) by smtp.gmail.com with ESMTPSA id p5-20020ac24ec5000000b0048abf3a550asm102806lfr.224.2022.07.27.05.35.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Jul 2022 05:35:25 -0700 (PDT) Message-ID: <7a0477a0-9f0f-87d6-4070-30321745f4cc@linaro.org> Date: Wed, 27 Jul 2022 14:35:24 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Subject: Re: [PATCH v2 1/2] dt-bindings: riscv: Add optional DT property riscv,timer-can-wake-cpu Content-Language: en-US To: Anup Patel Cc: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Daniel Lezcano , Thomas Gleixner , Andrew Jones , Atish Patra , Samuel Holland , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org References: <20220727114302.302201-1-apatel@ventanamicro.com> <20220727114302.302201-2-apatel@ventanamicro.com> <372e37bf-ac90-c371-ad9e-b9c18e1cc059@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 27/07/2022 14:21, Anup Patel wrote: > On Wed, Jul 27, 2022 at 5:37 PM Krzysztof Kozlowski > wrote: >> >> On 27/07/2022 13:43, Anup Patel wrote: >>> We add an optional DT property riscv,timer-can-wake-cpu which if present >>> in CPU DT node then CPU timer is always powered-on and never loses context. >>> >>> Signed-off-by: Anup Patel >>> --- >>> Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ >>> 1 file changed, 6 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml >>> index d632ac76532e..b60b64b4113a 100644 >>> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml >>> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml >>> @@ -78,6 +78,12 @@ properties: >>> - rv64imac >>> - rv64imafdc >>> >>> + riscv,timer-can-wake-cpu: >>> + type: boolean >>> + description: >>> + If present, the timer interrupt can wake up the CPU from >>> + suspend/idle state. >> >> Isn't this a property of a timer, not CPU? IOW, your timer node should >> have "wakeup-source" property. > > Historically (since the early days), we never had a timer node in the > RISC-V world. > >> >> Now that's actual problem: why the RISC-V timer is bound to "riscv" >> compatible, not to dedicated timer node? How is it related to actual CPU >> (not SoC)? > > The RISC-V timer is always present on all RISC-V platforms because Timer is always present also on ARMv8 (and ARMv7) yet it has its node. > the "time" CSR is defined by RISC-V privileged specification. The method > to program per-CPU timer events in either using SBI call or Sstc CSRs. Timer is still not part of CPU. Otherwise you are claiming here that CPU can wakeup CPU... > > Since, there is no dedicated timer node, we use CPU compatible string > for probing the per-CPU timer. Next time you add a properties: riscv,saata-can-wake-cpu riscv,usb-can-wake-cpu riscv,interrupt-controller-can-wake-cpu and so on and keep explaining that "historically" you did not define separate nodes, so thus must be in CPU node. You need to properly reflect hardware in the DTS instead of such hacks. Best regards, Krzysztof