From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 578ADC2DA; Fri, 22 Dec 2023 08:19:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="BFZ+o1oO" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BLNuE0o013061; Fri, 22 Dec 2023 08:18:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= message-id:date:mime-version:subject:to:cc:references:from :in-reply-to:content-type:content-transfer-encoding; s= qcppdkim1; bh=oiQ4ggoRxYTu3eH4divA9Q4c/SxtVHUkob3xWwNJWn4=; b=BF Z+o1oOVlKrVvvQQg6v8p0dR6C+uIF227mzgLRb2hKwsu0L1SdOm/vpQ6RT/lP4jM Oy2HizlxdzJKnyp16ZYW7L00BWlSpFBx720+kypcHPww3XcLIyYfpPGU0LoI52eD XP5+g1+ffK4rNkxA/4uWUu2MuliAkCLiHA+/iyepFi24hhQku/GUXXarkI1fRYAy Gdr8uTmeQvGoLr8UQyGw0dsN7ATORum4kkCSAwfdFnFC6FpcJgLxqPhhJsY0jF9+ rbnxY35gymB5mXU5+K5cw8cGLdtWT35iDnhRKSvdRBcLdyV4hmF0N+lQ556O8Lc7 gdgBwTH+XnH2UycFj4Gw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3v4pte2d88-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Dec 2023 08:18:45 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BM8IiAH022621 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Dec 2023 08:18:44 GMT Received: from [10.253.15.135] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 22 Dec 2023 00:18:40 -0800 Message-ID: <7a162d14-6a7a-44f0-ab45-12abfea5dedd@quicinc.com> Date: Fri, 22 Dec 2023 16:18:38 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v3 01/11] scsi: ufs: qcom: Perform read back after writing reset bit Content-Language: en-US To: Andrew Halaney , Andy Gross , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Hannes Reinecke , Janek Kotas , Alim Akhtar , Avri Altman , Bart Van Assche CC: Will Deacon , , , , Manivannan Sadhasivam References: <20231221-ufs-reset-ensure-effect-before-delay-v3-0-2195a1b66d2e@redhat.com> <20231221-ufs-reset-ensure-effect-before-delay-v3-1-2195a1b66d2e@redhat.com> From: Can Guo In-Reply-To: <20231221-ufs-reset-ensure-effect-before-delay-v3-1-2195a1b66d2e@redhat.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 6LkedyX4POhGTBDl0VUihjQbUT__LY3a X-Proofpoint-ORIG-GUID: 6LkedyX4POhGTBDl0VUihjQbUT__LY3a X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 clxscore=1011 priorityscore=1501 malwarescore=0 impostorscore=0 phishscore=0 suspectscore=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312220058 On 12/22/2023 3:09 AM, Andrew Halaney wrote: > Currently, the reset bit for the UFS provided reset controller (used by > its phy) is written to, and then a mb() happens to try and ensure that > hit the device. Immediately afterwards a usleep_range() occurs. > > mb() ensure that the write completes, but completion doesn't mean that > it isn't stored in a buffer somewhere. The recommendation for > ensuring this bit has taken effect on the device is to perform a read > back to force it to make it all the way to the device. This is > documented in device-io.rst and a talk by Will Deacon on this can > be seen over here: > > https://youtu.be/i6DayghhA8Q?si=MiyxB5cKJXSaoc01&t=1678 > > Let's do that to ensure the bit hits the device. By doing so and > guaranteeing the ordering against the immediately following > usleep_range(), the mb() can safely be removed. > > Fixes: 81c0fc51b7a7 ("ufs-qcom: add support for Qualcomm Technologies Inc platforms") > Reviewed-by: Manivannan Sadhasivam > Signed-off-by: Andrew Halaney > --- > drivers/ufs/host/ufs-qcom.h | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h > index 9dd9a391ebb7..b9de170983c9 100644 > --- a/drivers/ufs/host/ufs-qcom.h > +++ b/drivers/ufs/host/ufs-qcom.h > @@ -151,10 +151,10 @@ static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) > ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, UFS_PHY_SOFT_RESET, REG_UFS_CFG1); > > /* > - * Make sure assertion of ufs phy reset is written to > - * register before returning > + * Dummy read to ensure the write takes effect before doing any sort > + * of delay > */ > - mb(); > + ufshcd_readl(hba, REG_UFS_CFG1); > } > > static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba) > @@ -162,10 +162,10 @@ static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba) > ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, 0, REG_UFS_CFG1); > > /* > - * Make sure de-assertion of ufs phy reset is written to > - * register before returning > + * Dummy read to ensure the write takes effect before doing any sort > + * of delay > */ > - mb(); > + ufshcd_readl(hba, REG_UFS_CFG1); > } > > /* Host controller hardware version: major.minor.step */ > Reviewed-by: Can Guo