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Thu, 15 Oct 2026 07:21:10 -0700 (PDT) X-Received: by 2002:a05:6122:650b:b0:5e0:2ba:5a06 with SMTP id 71dfb90a1353d-5e91f576816mr4067389e0c.4.1792074069533; Thu, 15 Oct 2026 07:21:09 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c3ed6bea942sm131088866b.11.2026.10.15.07.21.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 Oct 2026 07:21:08 -0700 (PDT) Message-ID: <7a6ef006-cb76-4e4b-bd31-886af708b375@oss.qualcomm.com> Date: Thu, 15 Oct 2026 16:21:04 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/3] clk: qcom: dprxcc: Add Nord DPRX clock controller support To: Taniya Das , Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Abel Vesa Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa References: <20260924-nords_dprx-v2-0-fa4364e087ef@oss.qualcomm.com> <20260924-nords_dprx-v2-3-fa4364e087ef@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260924-nords_dprx-v2-3-fa4364e087ef@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: ZJy154jc5wa5vK7osT3OIpvCMCcAX_tD X-Proofpoint-ORIG-GUID: ZJy154jc5wa5vK7osT3OIpvCMCcAX_tD X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE1MDA1NyBTYWx0ZWRfX6uRu+TJAtySb HjWrkPpAX4K08WlWqeSdXwj8U5oRV40nDWSTf+2XhRjpAmczpGAX2613bP5ZbQfPPF4vEf7s8Sv 3/4SmZ1aK6RZSXuyDjYShraqkkvqh7Q= X-Authority-Analysis: v=2.4 cv=TbQDJhQh c=1 sm=1 tr=0 ts=6ad0e157 cx=c_pps a=N1BjEkVkxJi3uNfLdpvX3g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=2d2XUzBh9Lae0zXQoI4A:9 a=QEXdDO2ut3YA:10 a=crWF4MFLhNY0qMRaF8an:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE1MDA1NyBTYWx0ZWRfXyhW586b5HZHo bz6+1G8lEC4Le2iU4B6l9Z06A/xyAFDla9LpZDn3dFX93KXqSkLDFYP7c3sSPFv1iRa13iBeSj/ Hb01dHq6KeF+s36u3zs+z7rdLEL0N8dfj6CP4ECUDB/KtLLa6I9FNuCpuYYpgR7eJJ7UEgrkQVf poPhB6D/11NoyYmcw3rhOsFdVeAr+UH1C6EDKD7DHAB3RV1et7sWQCTmU11t7SMEeNNrUBJ8j8L Pod6sSdZ0CcG7R02/HyUK5eKPXagjwd29ihh3VFc4Dwgv1iATUiC3qOVzEPF+F/7dsaIqNjN3TM u6LmmCL/TlKRROCKCS2lb318wjANRsD3HfL2FXJ8e8hrIFawE9Yu9OuzANMl1Nibc1C/RByqE5W 4KBw9T2LToNdvAIfvmxy9GVHnQHWNW3I0PTplhjJk8Egy32V9MWBBYRRiPt0AAHz3afnudImxzU 4dwy4Zokxkf9U4I4xuw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-14_01,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 spamscore=0 clxscore=1015 impostorscore=0 phishscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610150057 On 9/23/26 9:21 PM, Taniya Das wrote: > Add support for the DisplayPort Receiver (DPRX) clock controllers on > Nord devices. There are two identical DPRX clock controller > instances (DPRX0 and DPRX1), each providing clocks for the DPRX core, > audio, AHB and video memory paths, along with core PLLs. > > Reviewed-by: Abel Vesa > Signed-off-by: Taniya Das > --- [...] > + /* > + * Configure cdiv 20 for core aud and 11 for core ahb clks of DPRX CC > + */ Nit: this fits in a /* single-line comment */ > + regmap_write(regmap, dprx_1_dprx_cc_core_aud_div_clk_src.reg, 0x13); > + regmap_write(regmap, dprx_1_dprx_cc_core_ahb_div_clk_src.reg, 0x0A); Hex should be lowercase, but preferably please define some sort of a bitfield that this value is written into and run regmap_update_bits() You should also set `.use_rpm = true` Konrad