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Fri, 20 Sep 2024 18:49:26 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.163 Received: from [10.32.65.165] (10.32.65.165) by ZXBJMBX03.zhaoxin.com (10.29.252.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 20 Sep 2024 18:42:20 +0800 Message-ID: <7a80b9f5-9503-45fa-bbf4-d0dfa97688ff@zhaoxin.com> Date: Fri, 20 Sep 2024 18:42:22 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/3] x86/mce: Add CMCI storm switching support for Zhaoxin To: "Zhuo, Qiuxu" , "tglx@linutronix.de" , "mingo@redhat.com" , "bp@alien8.de" , "dave.hansen@linux.intel.com" , "x86@kernel.org" , "hpa@zytor.com" , "Luck, Tony" , "linux-kernel@vger.kernel.org" , "linux-edac@vger.kernel.org" X-ASG-Orig-Subj: Re: [PATCH v3 3/3] x86/mce: Add CMCI storm switching support for Zhaoxin CC: "CobeChen@zhaoxin.com" , "TimGuo@zhaoxin.com" , "LeoLiu-oc@zhaoxin.com" , "Lyle Li" References: <20240910092652.13354-1-TonyWWang-oc@zhaoxin.com> <20240918055436.15551-1-TonyWWang-oc@zhaoxin.com> <20240918055436.15551-4-TonyWWang-oc@zhaoxin.com> Content-Language: en-US From: Tony W Wang-oc In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: ZXSHCAS1.zhaoxin.com (10.28.252.161) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Moderation-Data: 9/20/2024 6:49:24 PM X-Barracuda-Connect: ZXSHMBX1.zhaoxin.com[10.28.252.163] X-Barracuda-Start-Time: 1726829366 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.36:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 1503 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.130712 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- On 2024/9/20 17:17, Zhuo, Qiuxu wrote: > >> From: Tony W Wang-oc >> [...] >> Subject: [PATCH v3 3/3] x86/mce: Add CMCI storm switching support for >> [...] >> --- a/arch/x86/kernel/cpu/mce/zhaoxin.c >> +++ b/arch/x86/kernel/cpu/mce/zhaoxin.c >> @@ -63,3 +63,21 @@ void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) >> { >> intel_clear_lmce(); >> } >> + >> +void mce_zhaoxin_handle_storm(int bank, bool on) { >> + unsigned long flags; >> + u64 val; >> + >> + raw_spin_lock_irqsave(&cmci_discover_lock, flags); >> + rdmsrl(MSR_IA32_MCx_CTL2(bank), val); >> + if (on) { >> + val &= ~(MCI_CTL2_CMCI_EN | >> MCI_CTL2_CMCI_THRESHOLD_MASK); >> + val |= CMCI_STORM_THRESHOLD; >> + } else { >> + val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK; >> + val |= (MCI_CTL2_CMCI_EN | cmci_threshold[bank]); >> + } >> + wrmsrl(MSR_IA32_MCx_CTL2(bank), val); >> + raw_spin_unlock_irqrestore(&cmci_discover_lock, flags); } > > Are there any reasons or comments why it needs to disable/enable the CMCI interrupt > here during a CMCI storm on/off? If not, then reuse mce_intel_handle_storm() to avoid > duplicating the code. > As explained in another email. The reason is actually mentioned in the cover letter: "because Zhaoxin's UCR error is not reported through CMCI", and we want to disable CMCI interrupt when CMCI storm happened. Sincerely TonyWWang-oc