Re: [PATCH 2/2] cpufreq: CPPC: Fix error handling in cppc_scale_freq_workfn()

[Jie Zhan <zhanjie9@hisilicon.com>]

On 01/08/2025 16:58, Prashant Malani wrote:
> Hi Jie,
> 
> On Thu, 31 Jul 2025 at 01:32, Jie Zhan <zhanjie9@hisilicon.com> wrote:
>>
>>
>>
>> On 31/07/2025 06:34, Prashant Malani wrote:
>>
>> Hi Prashant,
>>
>> The perf counters could return 0 when a CPU is enters a low-power idle
>> state, e.g. reset or powered down, and the perf counters are in the system
>> memory space (the target CPU is not woken up unfortunately).
>>
> 
> Thanks for the clarification. Reset and powered down are not typically
> considered "low-power idle states".
Actually, power down and reset is a common low-power idle state defined in
ACPI spec and implemented on Intel chips.
Some quick references:
[1] ACPI spec 6.5, 8 PROCESSOR CONFIGURATION AND CONTROL
https://uefi.org/sites/default/files/resources/ACPI_Spec_6_5_Aug29.pdf
Also, the C1, C2, C3 states are refered as Clock Gated, Retention, and
Power Down respectively in 8.4.3 Lower Power Idle States.
[2] Intel 3rd gen Xeon Scalable, the C6 state.
https://www.intel.com/content/www/us/en/content-details/637748/power-management-technology-overview-technology-guide.html?wapkw=c-state

Nevertheless, it's still not widely supported in practice, so I understand
what you said.
> Please re-word your commit message to specifically call out the "reset and
> powered-down" CPU states.
Sure.  I'll try to make it a bit more straightforward in V2.
> 
> This begs the question: why is this work function being scheduled
> for CPUs that are in reset or offline/powered-down at all?
> IANAE but it sounds like it would be better to add logic to ensure this
> work function doesn't get scheduled/executed for CPUs that
> are truly offline/powered-down or in reset.
Yeah good question.  We may discuss that on your thread.
> 
> BR,
> 
Thanks!
Jie