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Wed, 22 Jul 2026 04:03:52 -0700 (PDT) X-Received: by 2002:a17:90b:3f85:b0:366:10f1:3d91 with SMTP id 98e67ed59e1d1-38e4b3dc094mr21959548a91.1.1784718231978; Wed, 22 Jul 2026 04:03:51 -0700 (PDT) Received: from [10.218.5.114] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38eb2eb81d4sm271176a91.14.2026.07.22.04.03.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 Jul 2026 04:03:51 -0700 (PDT) Message-ID: <7aa3a96b-d1ed-4686-b38a-85304ec61425@oss.qualcomm.com> Date: Wed, 22 Jul 2026 16:33:21 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/4] arm64: dts: qcom: shikra: Add support for AudioCoreCC and AudioCoreCSR nodes To: Dmitry Baryshkov Cc: Konrad Dybcio , Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, mohammad.rafi.shaik@oss.qualcomm.com References: <20260708-shikra-audiocorecc-v2-0-b320d822cdd0@oss.qualcomm.com> <20260708-shikra-audiocorecc-v2-4-b320d822cdd0@oss.qualcomm.com> <71576059-b5cd-401e-b4b0-c1784f24ba46@oss.qualcomm.com> <81ac9bcb-65c8-4cd5-bc54-c350f24d06a8@oss.qualcomm.com> Content-Language: en-US From: Imran Shaik In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=AJsSZ1gA c=1 sm=1 tr=0 ts=6a60a399 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=hEpXhfjFsWDJ7rCPAMoA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: O62-RtB_WLmdsMhehhOts2AwJWqwsq00 X-Proofpoint-ORIG-GUID: O62-RtB_WLmdsMhehhOts2AwJWqwsq00 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIyMDEwNyBTYWx0ZWRfX5bjJFqyLkCQk LuwIjIzwN6XXENrvUVfRODGEHV9aXAu6szjRmpZ+kmODsj7oIZ7S6MmOZ3Cc6cY9lnapm4YSILy dbcocRZRe0uFouN2U2dKE+tFRIYQMPc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIyMDEwNyBTYWx0ZWRfXzfGcTkOuUqB6 8LWtfnbYTTdPFB4+8+xwEuO78yXsnI93PPqT8tBe1OHg3XTdcWVzwQG73yq48v/qu5QJZcErZjq UlhZF9lSR6VvUFp5G1gdn1BbtNG5mJjBfRvK7IG4idqom7uczqBwKu8LB5s1zz/y+Fr2EBqyyNE RDt+Diov/Y7l2s8KhOZw+htH9cYNK0DdRsMofNpmgboE1bhHcTk+2NGCgcI6PyYhnbBI2qnc8fo dfHieroqOj2VStIxrTS+Sc1cGm9Ppb1W4tay2HzDwg7hmomsxLAk/gbMaOm+pLkfnB3zSZnv7dX 9SSofzmKEGwCWuK8FPY5koPWyKXIas8lFhm3p3ytA7UBtvgF/eVxg7aLRiTUTYc6bMcADSLaM8t Uh64fYnThJttlLlSR59EXxtdFtH5NRZj4iZdNtBAPHhSNlRS/e/0IqHZJFDRIPUQmroTdNcSCxV Ah4TYJaFKYYPdEfwQHw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-22_03,2026-07-21_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607220107 On 22-07-2026 11:54 am, Dmitry Baryshkov wrote: > On Mon, Jul 13, 2026 at 06:01:34PM +0530, Imran Shaik wrote: >> >> >> On 13-07-2026 05:44 pm, Konrad Dybcio wrote: >>> On 7/13/26 2:07 PM, Imran Shaik wrote: >>>> >>>> >>>> On 09-07-2026 05:30 pm, Konrad Dybcio wrote: >>>>> On 7/8/26 8:25 PM, Imran Shaik wrote: >>>>>> Add support for Audio Core Clock Controller (AudioCoreCC) and Audio Core >>>>>> CSR nodes on Qualcomm Shikra SoC. The Audio Core Clocks and Resets support >>>>>> differs across Shikra variants based on Audio subsystem enablement as >>>>>> follows: >>>>>> - CQM variant: The QAIF driver runs on HLOS, hence both clocks and resets >>>>>> are required to be supported on HLOS. >>>>>> - CQS variant: The QAIF driver runs on the Modem, and required clocks are >>>>>> handled on Modem, so from HLOS only resets are needed. >>>>>> - IQS variant: no soundwire codes, hence no clocks/resets are needed. >>>>>> >>>>>> Signed-off-by: Imran Shaik >>>>>> --- >>>>> >>>>> For the sake of simplification, can the resets be enabled >>>>> globally by default? >>>>> >>>> >>>> By default (PoR), those resets are under HW control. For audio use cases, software desserts/asserts for switching to SW control. Hence, these cannot be enabled globally by default. >>> >>> What does enabling the provider node have to do with changing the >>> state of the resources? >>> >> >> My bad, I interpreted it in wrong way. >> >> We have IQS variant, where we don't have the soundwire codes, and hence the >> respective clocks/resets are not required to be supported. Due to this, I >> have kept the status disabled, and enabling only where it is required. > > Would it make sense to do it differently - disable them for the IQS? Yeah, we can keep the audiocore_csr node enabled by default and disable it in the IQS variant. But Konrad suggested to keep it globally enabled and not disable in IQS variant for simplification since no one will consume those resets in the IQS variant and no functional impact. Please suggest which approach to follow here. > Is SoundWire not supported on the IQS at all or is it not a part of the > EVK? > As per my discussion with the Audio team, the IQS EVK board has no soundwire based audio codec connected. Actually, in the IQS hardware the AudioCoreCSR registers are present, but based on the Audio requirements we are not supporting it in IQS variant. Thanks, Imran >> >>> FWIW there's nothing like reset_sync_state >>> >> >> Sure, I can keep the audiocore_csr node enabled by default. >> >>> Konrad >> >