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Thu, 30 Apr 2026 00:19:34 -0700 (PDT) Message-ID: <7aa439cc-02a6-4b80-84be-1358ba8a6d60@linaro.org> Date: Thu, 30 Apr 2026 08:19:32 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/4] clk: qcom: camcc-glymur: Add camera clock controller driver To: Jagadeesh Kona , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio References: <20260429-glymur_camcc-v2-0-0c3fd1977869@oss.qualcomm.com> <20260429-glymur_camcc-v2-2-0c3fd1977869@oss.qualcomm.com> Content-Language: en-US From: Bryan O'Donoghue In-Reply-To: <20260429-glymur_camcc-v2-2-0c3fd1977869@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 29/04/2026 15:14, Jagadeesh Kona wrote: > +/* 1200.0 MHz Configuration */ > +static const struct alpha_pll_config cam_cc_pll0_config = { > + .l = 0x3e, > + .alpha = 0x8000, > + .config_ctl_val = 0x25c400e7, > + .config_ctl_hi_val = 0x0a8060e0, > + .config_ctl_hi1_val = 0xf51dea20, > + .user_ctl_val = 0x00008408, > + .user_ctl_hi_val = 0x00000002, > +}; Could we start defining these bits intead of stuffing magic numbers ? I can't imagine a PLL setting is commercially sensitive and even if it is.. There's a difference between someone in the community doing a port of a downstream configuration where the bits aren't documented and a vendor doing upstreaming where it the vendor has control. What does 0x0a8060e0 actually mean and - yes its more work but, why can't we define those bits and bit-fields ? --- bod