From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB3531A4F12 for ; Fri, 7 Feb 2025 09:21:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738920086; cv=none; b=JNlj5dkphO4JAWn7mYH/KkGcFKVcKYZcFC4U88OPd7ST7L8knq6uMfMPJnX/QR7uy9P2VGHXX3Bo8aBGHvAOXVTWupABkHICpnP79/4Y2wEakBEsVxksd65PWgupZRzlrsNi8FIAQq+T4vHFxN6a69ILBV/JD43YqfOyah+Dn+o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738920086; c=relaxed/simple; bh=I+m5NFphToaBU7KuM1MYybzmSrg3x16TgEyyHHWiTQY=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=smIRVF+B8GTQrZMtgHZ9OsV5iHWD4rwrOpBT9b0gPfi6YGTdHE7fPe8OOrQJL/fQyEc2Bh39q21Wn5XdwAmXHujnCJsgox2o7RRWWPSv/Mj4L995GLsxHtxbqenw7/IvseGGbOZysta1jd2NLkEVbbNOVetCxLtoU7tVaSTPzes= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=qvkOU91T; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="qvkOU91T" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-436249df846so12175185e9.3 for ; Fri, 07 Feb 2025 01:21:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738920082; x=1739524882; darn=vger.kernel.org; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=9tiH9b+H/9t/xpf0NWHkN82z4SsEthrDvr6Ide4MKv0=; b=qvkOU91TKwXhl3wwXeHbSANaUwtiNtlRtC+UiUeWYkITOEGsdrleTAPtqmKkTqD7EG 8OKunAgQ/SgTNK1MY6uJR2OE20OgZYo15aCnb7UH8o9+eQIIpVUwIIyrEJ/Wz129x7sV BVKbugM0+qYln6USEdUnyuosGvUTKp2kDhrYlw7VGFnnF8h7XX0nmPa/XYxIGb4e6Bn/ gE4EvuSIHLs+zv1B//il1qSjWwTjZKPhfpdDjsMmXwjcLWtC+gY8MNPio3f/VFAvPnt8 OAjIu5rHmJ/2up3i97w7OPMjf1Fgo7Yw1u8/JX1BmSzqmUUE8/9J1JSZys+EiUs6RLcy 8g6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738920082; x=1739524882; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=9tiH9b+H/9t/xpf0NWHkN82z4SsEthrDvr6Ide4MKv0=; b=xEDtWr0ltaAb/kDY9iJ5OPV3U2u8caWBhetUdtIjHxFGiokOZ+4FYALw2+MUoS0kDI zqgYXxaFfCBIb7O9X/0Nl4mmY2+ftwkNQZ8F/0Vh6D8ANoBjWcV/XePbhzzR4czF51ol xkcbvX+h8fq8FGY6jTJ8/qR/6avhCIpHCcXnmaU5xSN/30yQDo7vSdqvGZC35bI4pV0B VqoXVdKhxqCnA954KAXLDfCxFGBdY4No2GqgBldL8Z7jI7r0diAzSPTF/OfmcO6M+aTa k/l+fyKje2kRSSh3V5jO+siTL+0gKxQPDVodjiF98LjwKnpA6MZFcXBZeud//8J3bagJ Ef7Q== X-Forwarded-Encrypted: i=1; AJvYcCUJgfuFsp9v/d6K88yeB19W/DJxVWhodcweG0aqMgEOoqInlNEqxjtukpmLe77Q0SB781QyBSVI10+P6QU=@vger.kernel.org X-Gm-Message-State: AOJu0YwsdH82KySkCiJ6rp7826quZYJdKtQVLaRjY6ek2NDcV50BytE3 3nqDxDsHQVkdzTyFje3M2jfpJ6bR7WEGfYu59JpQztR8ABmYUh6Ewb1TlWLR4FQ= X-Gm-Gg: ASbGncuWpE66PdQ70aK5K6mkZ0zI90yQ/57/7p7eP4cvrIeaHQNSebZo8jOPAaMMBBK oQ3+4ZY9LAEqAAqJ9nF8AvbwEZ/WDJ0cdFy7N5dzPvtgUEjQSytNnvVT6zqcfEVG6cvUocTNxRr buASFNfQqY7x1SZ9Hrd4424OKFYUgAM7ISqmGRYJKRy46rqyU5/+hHnsYsHTSzIhiIeek9OwLK5 2+KWGa+xwnkUO7wbP8T8lqlZFEzShjfdCBtupJGkFjT9OOcxIEa5VIHAnpCGAPstCa+jYd21pqk 3eaNjM23BsvuFGarDiTJSLmIMlw3bN+2Fs5b9/DsszSvb8fsVdgB9YzpQjer X-Google-Smtp-Source: AGHT+IECWFH7U0mArd280iuB70Vnw8HZQHKBAtWHAu5Pk2zNKD95w0WIBx5nMCf9e60ecld/9uOCGw== X-Received: by 2002:a05:600c:3c9b:b0:436:5fc9:30ba with SMTP id 5b1f17b1804b1-439249c385cmr21219595e9.29.1738920082212; Fri, 07 Feb 2025 01:21:22 -0800 (PST) Received: from ?IPV6:2a01:e0a:e17:9700:16d2:7456:6634:9626? ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439069290c7sm87180725e9.0.2025.02.07.01.21.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Feb 2025 01:21:21 -0800 (PST) Message-ID: <7aace8a9-0e62-4156-9c50-f7b399c4eba2@rivosinc.com> Date: Fri, 7 Feb 2025 10:21:20 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 06/21] RISC-V: Add Smcntrpmf extension parsing To: Atish Patra , Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> <20250205-counter_delegation-v4-6-835cfa88e3b1@rivosinc.com> Content-Language: en-US From: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= In-Reply-To: <20250205-counter_delegation-v4-6-835cfa88e3b1@rivosinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 06/02/2025 08:23, Atish Patra wrote: > Smcntrpmf extension allows M-mode to enable privilege mode filtering > for cycle/instret counters. However, the cyclecfg/instretcfg CSRs are > only available only in Ssccfg only Smcntrpmf is present. > > That's why, kernel needs to detect presence of Smcntrpmf extension and > enable privilege mode filtering for cycle/instret counters. > > Signed-off-by: Atish Patra > --- > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 3d6e706fc5b2..b4eddcb57842 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -102,6 +102,7 @@ > #define RISCV_ISA_EXT_SVADU 93 > #define RISCV_ISA_EXT_SSCSRIND 94 > #define RISCV_ISA_EXT_SMCSRIND 95 > +#define RISCV_ISA_EXT_SMCNTRPMF 96 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index c6da81aa48aa..8f225c9c3055 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -390,6 +390,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), > __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), > __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), > + __RISCV_ISA_EXT_DATA(smcntrpmf, RISCV_ISA_EXT_SMCNTRPMF), > __RISCV_ISA_EXT_DATA(smcsrind, RISCV_ISA_EXT_SMCSRIND), > __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM), > __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_exts), > Looks good to me. Reviewed-by: Clément Léger Thanks, Clément