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Fri, 09 Oct 2026 03:09:53 -0700 (PDT) X-Received: by 2002:a05:7022:3b87:b0:148:80d4:84b0 with SMTP id a92af1059eb24-16a60de2f7fmr2202142c88.23.1791540593160; Fri, 09 Oct 2026 03:09:53 -0700 (PDT) Received: from [10.218.39.50] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3537ca1cc25sm7332804eec.8.2026.10.09.03.09.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Oct 2026 03:09:52 -0700 (PDT) Message-ID: <7ab6eab6-ec6e-47dc-b387-eb380e2e365c@oss.qualcomm.com> Date: Fri, 9 Oct 2026 15:39:45 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5] iommu/io-pgtable-arm: Add support for contiguous hint bit To: Jason Gunthorpe , Daniel Mentz Cc: Will Deacon , Robin Murphy , "Joerg Roedel (AMD)" , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Prakash Gupta References: <20260921-iommu_contig_hint-v5-1-e7fbd1c3774d@oss.qualcomm.com> <20260924001502.GO1540250@ziepe.ca> <20260924225340.GC16465@ziepe.ca> Content-Language: en-US From: Vijayanand Jitta In-Reply-To: <20260924225340.GC16465@ziepe.ca> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=E+1YNqdl c=1 sm=1 tr=0 ts=6ac8bd72 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=VwQbUJbxAAAA:8 a=Ikd4Dj_1AAAA:8 a=9jRdOu3wAAAA:8 a=EUspDBNiAAAA:8 a=YC-9j5RmPirwrlDSig8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 a=ZE6KLimJVUuLrTuGpvhn:22 X-Proofpoint-GUID: PHdz7G8XAyXYMKK_smvOdIdH9cWQqfX5 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA5MDA0MCBTYWx0ZWRfX4lsnofbE+xNk ZUIX8wVUBmZyQjr/p9GBZarsc1pEYA5e/5NkmAPecpdzWPLkI618FpNCzQp+5J16tmiDPniwzfA PZTdJnVnUTESbtFX1h2261rcXTNTQmBChDdH5oEYij+YH+xheFfTVwYiDb2BCBKwV8mo0gTR7Eq vAvdnEx4uGkwuv1e0Txi/QJQ9jKmFgTh/3w/zjbA9JUUbuV6zIO5L6f6Ck9Y8cW1LR8/BhTk3zQ 1fRxYjRm4QY9pyOoju0QpLncU7fkevYj0x5i+VsKf/Lo8EVuNvzHoevc2xU7WQUwP3+XpEOvOgF VZBBJrM8ioI7gh0WP7O32cVXwO6vo3HohDcR0YlP6v4JVG0k+3X2truBieN9weWVk/6rV6JpI4p uEFIvV9zV0WPYh43xj8XCOB/ZBNSei7mdVfahPSQNMSfI0gYl/LIh/gPphTqyr0tKgAJuHiUfL9 5JpUYUg+59yyoOSflVA== X-Proofpoint-ORIG-GUID: PHdz7G8XAyXYMKK_smvOdIdH9cWQqfX5 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA5MDA0MCBTYWx0ZWRfX+ZYeZdSPB3Zk FdcUBi4mUNko4OqFNrrWJXZIXEbnfxkEysmznmwfwGG9HLxdCrosaQTHi1KU6YfJXBzj+ZDZuL2 CABj32O8d259UqoBlb2WsQiz8GNGe+U= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-09_03,2026-10-08_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 suspectscore=0 malwarescore=0 spamscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610020000 definitions=main-2610090040 On 9/25/2026 4:23 AM, Jason Gunthorpe wrote: > On Thu, Sep 24, 2026 at 11:49:50AM -0700, Daniel Mentz wrote: >> On Wed, Sep 23, 2026 at 5:15 PM Jason Gunthorpe wrote: >>> >>> On Mon, Sep 21, 2026 at 04:44:07PM +0530, Vijayanand Jitta wrote: >>>> From: Prakash Gupta >>>> >>>> Add support for the contiguous hint (CONT) bit in ARM LPAE page tables. >>>> When a set of consecutive PTEs map a naturally aligned contiguous block of >>>> memory, set CONT on every descriptor in that group so the hardware can >>>> combine translations and improve TLB reach. >>>> >>>> Advertise the supported CONT group sizes in pgsize_bitmap. Callers select >>>> those sizes through the normal page-size selection path; io-pgtable-arm >>>> then installs the corresponding tagged descriptors directly. A partial >>>> unmap of a tagged CONT group is rejected before modifying any descriptor, >>>> so a rejected request cannot leave the group partly unmapped. >>>> >>>> The IO_PGTABLE_QUIRK_ARM_NO_CONT_HINT quirk allows SMMU drivers to disable >>>> CONT support for hardware with implementation-specific errata. >>> >>> smmuv3 has this errata, it must be disabled there too. I didn't notice >>> it in this patch? >> >> SMMU is an architecture specification. I am not aware of errors in >> this architecture specification that would preclude the usage of the >> contiguous bit. I understand that Arm MMU-700 has the following >> erratum >> >> 3777127 Under invalidation in TBU possible when using contiguous page >> table entries > > And a neoverse one too. > >> The recommended workaround is described as >> >> "Ensure that contiguous page tables are removed using a single range >> invalidation. Arm recommends using range invalidations to remove >> contiguous entries anyway for performance reasons." >> >> and I believe we are already doing this. > > No we aren't. Go read my fix on this: > > https://lore.kernel.org/linux-iommu/1-v7-e84261bbe7cd+2ea80b-smmu_tlbi_jgg@nvidia.com/ > > I have another patch that fixes it for iommu domain mappings too. > > Jason Sure , will disable it for smmuv3 for now. Thanks, Vijay