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AJvYcCWT4x5/CEu2qV9wlU1fR+0ewOq9CGSPOvGLL5eQp+LM5ZeW2eGZU4JgrHVeIpgj1gW2RsOhlVV2utyEGcCDNPchqvKUYwAXSHWJgq3t X-Gm-Message-State: AOJu0YxjXfljdU4pViPD3gwb4VgwpG+zoe5H3hC4K4eFwGpLpYMU3kjO HNhoqu5s+elH5nlRMvFH49APZ6O6g5x60C6J9Pe6leTxx3YFhhFN1babh8+TFdM= X-Google-Smtp-Source: AGHT+IEwPAYueYsYBU7iXqBEMRFmuAd1MLK051xLXmuVq1c5N6cvZaOPH+qJWxXVW1W7c7sUfLOy2Q== X-Received: by 2002:a05:6808:211b:b0:3d2:16c6:651a with SMTP id 5614622812f47-3d6b568709cmr9465278b6e.53.1719850318992; Mon, 01 Jul 2024 09:11:58 -0700 (PDT) Received: from [100.64.0.1] ([147.124.94.167]) by smtp.gmail.com with ESMTPSA id af79cd13be357-79d692945b4sm357969185a.57.2024.07.01.09.11.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 Jul 2024 09:11:58 -0700 (PDT) Message-ID: <7ab7d629-6993-4cad-b5b7-62bddfc74a49@sifive.com> Date: Mon, 1 Jul 2024 11:11:55 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 03/13] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree To: Conor Dooley , Charlie Jenkins Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , peterlin@andestech.com References: <20240619-xtheadvector-v3-0-bff39eb9668e@rivosinc.com> <20240619-xtheadvector-v3-3-bff39eb9668e@rivosinc.com> <0cc13581-5cc4-4a25-a943-7a896f42da4c@sifive.com> <20240701-prancing-outpost-3cbce791c554@spud> Content-Language: en-US From: Samuel Holland In-Reply-To: <20240701-prancing-outpost-3cbce791c554@spud> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Conor, Charlie, On 2024-07-01 11:07 AM, Conor Dooley wrote: > On Mon, Jul 01, 2024 at 10:27:01AM -0500, Samuel Holland wrote: >> On 2024-06-19 6:57 PM, Charlie Jenkins wrote: >>> The D1/D1s SoCs support xtheadvector so it can be included in the >>> devicetree. Also include vlenb for the cpu. >>> >>> Signed-off-by: Charlie Jenkins >>> Reviewed-by: Conor Dooley >>> --- >>> arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++- >> >> The other C906/C910/C920-based SoCs need devicetree updates as well, although >> they don't necessarily need to be part of this series: >> >> - sophgo/cv18xx.dtsi >> - sophgo/sg2042-cpus.dtsi >> - thead/th1520.dtsi > > Yeah, I think I pointed that out before with the same "escape hatch" of > it not needing to be in the same series. > >> >>> 1 file changed, 2 insertions(+), 1 deletion(-) >>> >>> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi >>> index 64c3c2e6cbe0..6367112e614a 100644 >>> --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi >>> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi >>> @@ -27,7 +27,8 @@ cpu0: cpu@0 { >>> riscv,isa = "rv64imafdc"; >> >> The ISA string should be updated to keep it in sync with riscv,isa-extensions. > > This probably looks like this cos I said that the kernel shouldn't parse > vendor extensions from "riscv,isa". My rationale was that we have > basically no control of what a vendor extension means in riscv,isa so > we shouldn't parse them from it (so marginally worse than standard > extensions, where it means what the spec says except when it doesn't). > > Given how we implement the parsing, it also meant we weren't implying > meanings for vendor extensions ACPI-land, where we also can't ensure the > meanings or that they remain stable. That change is in a different > series: > https://patchwork.kernel.org/project/linux-riscv/patch/20240609-support_vendor_extensions-v2-1-9a43f1fdcbb9@rivosinc.com/ > > Although now that I think about it, this might break xandespmu... I > dunno if the Andes guys switched over to using the new property outside > of the single dts in the kernel tree using their SoC. We could > potentially special-case that extension if they haven't - but my > position on this mostly is that if you want to use vendor extensions you > should not be using riscv,isa (even if the regex doesn't complain if you > add them). I'd like to leave the code in the other patch as-is if we can > help it. > > I added Yu Chien Peter Lin here, maybe they can let us know what they're > doing. OK, that makes sense to me. Then please ignore my original comment. Regards, Samuel