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The 1 ms upper bound is a software limit for a stuck PLL, > not a TRM-derived value; Zynq PLL lock is still expected well > within that window. > > Changes in v2: > - Use BIT(clk->lockbit) > - Name the poll delay/timeout constants > - Clarify the 1 ms bound in the commit message > > Fixes: 3682af46d55f ("clk: zynq: Factor out PLL driver") > Signed-off-by: Linkai Gong > --- > drivers/clk/zynq/pll.c | 15 ++++++++++++--- > 1 file changed, 12 insertions(+), 3 deletions(-) Tested-by: Michal Simek Thanks, Michal