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Sun, 15 Mar 2026 22:05:59 -0700 (PDT) X-Received: by 2002:a17:903:3905:b0:2ae:3d7d:d905 with SMTP id d9443c01a7336-2aecaa18fb8mr132301955ad.23.1773637559455; Sun, 15 Mar 2026 22:05:59 -0700 (PDT) Received: from [10.218.35.45] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2aece83ded9sm92962095ad.81.2026.03.15.22.05.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 15 Mar 2026 22:05:59 -0700 (PDT) Message-ID: <7ac68128-a3d2-4244-9435-a39f6eec1d1a@oss.qualcomm.com> Date: Mon, 16 Mar 2026 10:35:50 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/3] PCI: qcom: Program T_POWER_ON To: Manivannan Sadhasivam Cc: Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Jingoo Han , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com, quic_vbadigan@quicinc.com References: <20260311-t_power_on_fux-v3-0-9b1f1d09c6f3@oss.qualcomm.com> <20260311-t_power_on_fux-v3-3-9b1f1d09c6f3@oss.qualcomm.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE2MDAzNiBTYWx0ZWRfX3ohMYfHq7XFN 6d6Qe7tgG8tAb/LEYih/bUURQW6di9umtrR7Ubp/It8da1pkPBYDmwVJiOH+//jnvz9baLlpfF+ hunjgVfehcOMwP3RtgZmPHPjQBpebaZXGWZFOcpV3BKwBgo6SzjS9On2/6yFf7Vcb+WaLyiP0KX qVRURziwv1B61rASW6qHrXE3kv9BDq1eLZkldc9VO9o0BOUqUlRNCaZbynmJG3cZLSuVirjb7L2 aJS+GlgXaJcMHT72rCTIdQHd9pdl/u/p6nNuV+6Uyr3XI/xpTfxJA5h7uD+p0VCrX7qWmEv8cWq OffJWC55/aLymYgdHmmPYoasRS/iLVVbQIpCNjZHvOn4leujNBZpG9j5i6jNjy+i1P9q0EHwwK+ SZdL/OPAnRwqObXkigaeDG4uXwjsmP31kIqzA6Ekz6M9Ds1SBBhKLEsc7m1lVJ673KJh8QiGi8G rUEcBMhH2HM/cvJxVIg== X-Proofpoint-GUID: qPX4edCrbnSuF0UdXcQQXKcQaAfXh3QY X-Authority-Analysis: v=2.4 cv=SJJPlevH c=1 sm=1 tr=0 ts=69b78fb9 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=TGbq2H1_L8zW2zdi06cA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-ORIG-GUID: qPX4edCrbnSuF0UdXcQQXKcQaAfXh3QY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-16_02,2026-03-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603160036 On 3/16/2026 10:23 AM, Manivannan Sadhasivam wrote: > On Wed, Mar 11, 2026 at 06:10:40PM +0530, Krishna Chaitanya Chundru wrote: >> Some platforms have incorrect T_POWER_ON value programmed in hardware. >> Generally these will be corrected by bootloaders, but not all targets >> support bootloaders to program correct values due to that >> LTR_L1.2_THRESHOLD value calculated by aspm driver can be wrong, which >> can result in improper L1.2 exit behavior and if AER happens to be >> supported and enabled, the error may be *reported* via AER. >> >> Parse "t-power-on-us" property from each root port node and program them >> as part of host initialization using dw_pcie_program_t_power_on() before >> link training. >> >> This property in added to the dtschema here[1]. >> >> Signed-off-by: Krishna Chaitanya Chundru >> Link[1]: https://lore.kernel.org/all/20260205093346.667898-1-krishna.chundru@oss.qualcomm.com/ >> --- >> drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++ >> 1 file changed, 13 insertions(+) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >> index 67a16af69ddc75fca1b123e70715e692a91a9135..63d5628e988d3c07f42099c0d86e6b80fd54ce32 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -269,6 +269,7 @@ struct qcom_pcie_perst { >> struct qcom_pcie_port { >> struct list_head list; >> struct phy *phy; >> + u32 l1ss_t_power_on; >> struct list_head perst; >> }; >> >> @@ -1283,6 +1284,14 @@ static int qcom_pcie_phy_power_on(struct qcom_pcie *pcie) >> return 0; >> } >> >> +static void qcom_pcie_configure_ports(struct qcom_pcie *pcie) >> +{ >> + struct qcom_pcie_port *port; >> + >> + list_for_each_entry(port, &pcie->ports, list) >> + dw_pcie_program_t_power_on(pcie->pci, port->l1ss_t_power_on); >> +} >> + >> static int qcom_pcie_host_init(struct dw_pcie_rp *pp) >> { >> struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >> @@ -1317,6 +1326,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) >> dw_pcie_remove_capability(pcie->pci, PCI_CAP_ID_MSIX); >> dw_pcie_remove_ext_capability(pcie->pci, PCI_EXT_CAP_ID_DPC); >> >> + qcom_pcie_configure_ports(pcie); >> + >> qcom_pcie_perst_deassert(pcie); >> >> if (pcie->cfg->ops->config_sid) { >> @@ -1759,6 +1770,8 @@ static int qcom_pcie_parse_port(struct qcom_pcie *pcie, struct device_node *node >> if (ret) >> return ret; >> >> + of_property_read_u32(node, "t-power-on-us", &port->l1ss_t_power_on); >> + > Since this is going to be common for all controller drivers, it'd be good to > move this inside the dwc API. As this per root port, we can summit changes to merge first so that we can move this to dwc. - Krishna Chaitanya. > > - Mani >