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Fri, 24 Jan 2025 10:32:48 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50OAWlsa029918 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 24 Jan 2025 10:32:47 GMT Received: from [10.217.217.81] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 24 Jan 2025 02:32:39 -0800 Message-ID: <7aca503d-4a8f-4c3e-ae1e-b95d49c65a85@quicinc.com> Date: Fri, 24 Jan 2025 16:02:36 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/5] clk: qcom: lpassaudiocc-sc7280: Add support for LPASS resets for QCM6490 To: Krzysztof Kozlowski , Dmitry Baryshkov CC: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , , , , , , References: <20240816-qcm6490-lpass-reset-v1-0-a11f33cad3c5@quicinc.com> <20240816-qcm6490-lpass-reset-v1-2-a11f33cad3c5@quicinc.com> <67819a53-8e99-469b-a458-8c00034fec4a@kernel.org> <936f151e-6951-4dea-95ed-35374ab249cf@quicinc.com> <9b3350ba-eafe-4bb0-a6cc-f1b0a06d623e@kernel.org> <80ca3719-1c7f-4899-b533-faf3c9093444@kernel.org> Content-Language: en-US From: Taniya Das In-Reply-To: <80ca3719-1c7f-4899-b533-faf3c9093444@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 6Hdv-SzDf9oXrtu0F7zkqcEYraxVGl5M X-Proofpoint-ORIG-GUID: 6Hdv-SzDf9oXrtu0F7zkqcEYraxVGl5M X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-24_04,2025-01-23_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 suspectscore=0 clxscore=1015 priorityscore=1501 adultscore=0 spamscore=0 impostorscore=0 mlxlogscore=999 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501240076 On 9/16/2024 2:33 PM, Krzysztof Kozlowski wrote: > On 16/09/2024 10:55, Dmitry Baryshkov wrote: >> On Mon, Sep 16, 2024 at 10:33:21AM GMT, Krzysztof Kozlowski wrote: >>> On 13/09/2024 07:31, Taniya Das wrote: >>>> >>>> >>>> On 8/17/2024 2:55 PM, Krzysztof Kozlowski wrote: >>>>> On 16/08/2024 10:32, Taniya Das wrote: >>>>>> On the QCM6490 boards the LPASS firmware controls the complete clock >>>>>> controller functionalities. But the LPASS resets are required to be >>>>>> controlled from the high level OS. The Audio SW driver should be able to >>>>>> assert/deassert the audio resets as required. Thus in clock driver add >>>>>> support for the resets. >>>>>> >>>>>> Signed-off-by: Taniya Das >>>>>> --- >>>>>> drivers/clk/qcom/lpassaudiocc-sc7280.c | 23 +++++++++++++++++++---- >>>>>> 1 file changed, 19 insertions(+), 4 deletions(-) >>>>>> >>>>>> diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c >>>>>> index 45e726477086..b64393089263 100644 >>>>>> --- a/drivers/clk/qcom/lpassaudiocc-sc7280.c >>>>>> +++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c >>>>>> @@ -1,6 +1,7 @@ >>>>>> // SPDX-License-Identifier: GPL-2.0-only >>>>>> /* >>>>>> * Copyright (c) 2021, The Linux Foundation. All rights reserved. >>>>>> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. >>>>>> */ >>>>>> >>>>>> #include >>>>>> @@ -713,14 +714,24 @@ static const struct qcom_reset_map lpass_audio_cc_sc7280_resets[] = { >>>>>> [LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 }, >>>>>> }; >>>>>> >>>>>> +static const struct regmap_config lpass_audio_cc_sc7280_reset_regmap_config = { >>>>>> + .name = "lpassaudio_cc_reset", >>>>>> + .reg_bits = 32, >>>>>> + .reg_stride = 4, >>>>>> + .val_bits = 32, >>>>>> + .fast_io = true, >>>>>> + .max_register = 0xc8, >>>>>> +}; >>>>>> + >>>>>> static const struct qcom_cc_desc lpass_audio_cc_reset_sc7280_desc = { >>>>>> - .config = &lpass_audio_cc_sc7280_regmap_config, >>>>>> + .config = &lpass_audio_cc_sc7280_reset_regmap_config, >>>>>> .resets = lpass_audio_cc_sc7280_resets, >>>>>> .num_resets = ARRAY_SIZE(lpass_audio_cc_sc7280_resets), >>>>>> }; >>>>>> >>>>>> static const struct of_device_id lpass_audio_cc_sc7280_match_table[] = { >>>>>> - { .compatible = "qcom,sc7280-lpassaudiocc" }, >>>>>> + { .compatible = "qcom,qcm6490-lpassaudiocc", .data = &lpass_audio_cc_reset_sc7280_desc }, >>>>> >>>>> That's odd to see sc7280 reset added for qcm6490, but not used fot >>>>> sc7280 at all. Didn't you mean here lpass_audio_cc_qcm6409_desc? >>>>> >>>>> >>>> The resets descriptor(lpass_audio_cc_reset_sc7280_desc) is not part of >>>> the global clock descriptor(lpass_cc_sc7280_desc) as these are part of >>>> different regmaps. >>>> >>>> On a non-QCM6490(SC7280) boards the resets are registered after the >>>> global descriptor is registered. >>>> >>>> But on QCM6490 board we need to register only the reset descriptor and >>>> no clocks are to be handled/registered and thus passed the match data >>>> for QCM6490 boards only. >>> >>> Yeah, but why this is sc7280? >> >> Because it's more or less the same HW, different TZ and hyp firmware? >> > > Hm, ok, probably I missed something from the context. > Apologies for responding on this thread later than expected. Yes as Dmitry mentioned, it is the same HW, TZ and HYP firmware are different. > Best regards, > Krzysztof -- Thanks & Regards, Taniya Das.