From: Waiman Long <longman@redhat.com>
To: guoren@kernel.org, palmer@rivosinc.com, arnd@arndb.de,
peterz@infradead.org, boqun.feng@gmail.com,
Conor.Dooley@microchip.com, chenhuacai@loongson.cn,
kernel@xen0n.name, r@hev.cc, shorne@gmail.com
Cc: linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org,
linux-kernel@vger.kernel.org, Guo Ren <guoren@linux.alibaba.com>
Subject: Re: [PATCH V6 0/2] riscv: Support qspinlock with generic headers
Date: Tue, 21 Jun 2022 11:08:21 -0400 [thread overview]
Message-ID: <7adc9e19-7ffc-4b11-3e18-6e3a5225638f@redhat.com> (raw)
In-Reply-To: <20220621144920.2945595-1-guoren@kernel.org>
On 6/21/22 10:49, guoren@kernel.org wrote:
> From: Guo Ren <guoren@linux.alibaba.com>
>
> Enable qspinlock and meet the requirements mentioned in a8ad07e5240c9
> ("asm-generic: qspinlock: Indicate the use of mixed-size atomics").
>
> RISC-V LR/SC pairs could provide a strong/weak forward guarantee that
> depends on micro-architecture. And RISC-V ISA spec has given out
> several limitations to let hardware support strict forward guarantee
> (RISC-V User ISA - 8.3 Eventual Success of Store-Conditional
> Instructions):
> We restricted the length of LR/SC loops to fit within 64 contiguous
> instruction bytes in the base ISA to avoid undue restrictions on
> instruction cache and TLB size and associativity. Similarly, we
Does the 64 contiguous bytes need to be cacheline aligned?
Regards,
Longman
next prev parent reply other threads:[~2022-06-21 15:08 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-21 14:49 guoren
2022-06-21 14:49 ` [PATCH V6 1/2] asm-generic: spinlock: Move qspinlock & ticket-lock into generic spinlock.h guoren
2022-06-23 8:33 ` Arnd Bergmann
2022-06-23 9:17 ` Guo Ren
2022-06-21 14:49 ` [PATCH V6 2/2] riscv: Add qspinlock support guoren
2022-06-21 15:08 ` Waiman Long [this message]
2022-06-22 1:51 ` [PATCH V6 0/2] riscv: Support qspinlock with generic headers Guo Ren
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