From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 936E8C2D0A3 for ; Fri, 6 Nov 2020 15:30:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 36F2622202 for ; Fri, 6 Nov 2020 15:30:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727567AbgKFPaG (ORCPT ); Fri, 6 Nov 2020 10:30:06 -0500 Received: from disco-boy.misterjones.org ([51.254.78.96]:43348 "EHLO disco-boy.misterjones.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726812AbgKFPaF (ORCPT ); Fri, 6 Nov 2020 10:30:05 -0500 Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.94) (envelope-from ) id 1kb3gc-008Eeb-Vr; Fri, 06 Nov 2020 15:29:59 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Fri, 06 Nov 2020 15:29:58 +0000 From: Marc Zyngier To: Andre Przywara Cc: Will Deacon , Catalin Marinas , Ard Biesheuvel , Russell King , Lorenzo Pieralisi , Linus Walleij , linux-kernel@vger.kernel.org, Mark Brown , Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 3/5] ARM: implement support for SMCCC TRNG entropy source In-Reply-To: <20201105125656.25259-4-andre.przywara@arm.com> References: <20201105125656.25259-1-andre.przywara@arm.com> <20201105125656.25259-4-andre.przywara@arm.com> User-Agent: Roundcube Webmail/1.4.9 Message-ID: <7b36daa49c78d60dc788bbb3c9c1bdaa@misterjones.org> X-Sender: maz@misterjones.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: andre.przywara@arm.com, will@kernel.org, catalin.marinas@arm.com, ardb@kernel.org, linux@armlinux.org.uk, lorenzo.pieralisi@arm.com, linus.walleij@linaro.org, linux-kernel@vger.kernel.org, broonie@kernel.org, sudeep.holla@arm.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@misterjones.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2020-11-05 12:56, Andre Przywara wrote: > From: Ard Biesheuvel > > Implement arch_get_random_seed_*() for ARM based on the firmware > or hypervisor provided entropy source described in ARM DEN0098. > > This will make the kernel's random number generator consume entropy > provided by this interface, at early boot, and periodically at > runtime when reseeding. > > Cc: Linus Walleij > Cc: Russell King > Signed-off-by: Ard Biesheuvel > [Andre: rework to be initialised by the SMCCC firmware driver] > Signed-off-by: Andre Przywara > --- > arch/arm/Kconfig | 4 ++ > arch/arm/include/asm/archrandom.h | 64 +++++++++++++++++++++++++++++++ > 2 files changed, 68 insertions(+) > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index fe2f17eb2b50..06fda4f954fd 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -1667,6 +1667,10 @@ config STACKPROTECTOR_PER_TASK > Enable this option to switch to a different method that uses a > different canary value for each task. > > +config ARCH_RANDOM > + def_bool y > + depends on HAVE_ARM_SMCCC > + > endmenu > > menu "Boot options" > diff --git a/arch/arm/include/asm/archrandom.h > b/arch/arm/include/asm/archrandom.h > index a8e84ca5c2ee..f3e96a5b65f8 100644 > --- a/arch/arm/include/asm/archrandom.h > +++ b/arch/arm/include/asm/archrandom.h > @@ -2,9 +2,73 @@ > #ifndef _ASM_ARCHRANDOM_H > #define _ASM_ARCHRANDOM_H > > +#ifdef CONFIG_ARCH_RANDOM > + > +#include > +#include > + > +#define ARM_SMCCC_TRNG_MIN_VERSION 0x10000UL > + > +extern bool smccc_trng_available; > + > +static inline bool __init smccc_probe_trng(void) > +{ > + struct arm_smccc_res res; > + > + arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_VERSION, &res); > + if ((s32)res.a0 < 0) > + return false; > + if (res.a0 >= ARM_SMCCC_TRNG_MIN_VERSION) { > + /* double check that the 32-bit flavor is available */ > + arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_FEATURES, > + ARM_SMCCC_TRNG_RND32, > + &res); > + if ((s32)res.a0 >= 0) > + return true; > + } > + > + return false; > +} > + > +static inline bool __must_check arch_get_random_long(unsigned long *v) > +{ > + return false; > +} > + > +static inline bool __must_check arch_get_random_int(unsigned int *v) > +{ > + return false; > +} > + > +static inline bool __must_check arch_get_random_seed_long(unsigned > long *v) > +{ > + struct arm_smccc_res res; > + > + if (smccc_trng_available) { > + arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_RND32, 8 * sizeof(*v), &res); > + > + if (res.a0 != 0) > + return false; > + > + *v = res.a3; > + return true; > + } > + > + return false; > +} > + > +static inline bool __must_check arch_get_random_seed_int(unsigned int > *v) > +{ > + return arch_get_random_seed_long((unsigned long *)v); I don't think this cast is safe. At least not on 64bit. M. -- Who you jivin' with that Cosmik Debris?