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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b976cf49fa6sm528302166b.58.2026.03.16.02.24.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 16 Mar 2026 02:24:49 -0700 (PDT) Message-ID: <7b44e540-6ab1-4f41-a878-08f50fa9a5af@oss.qualcomm.com> Date: Mon, 16 Mar 2026 10:24:46 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 10/11] clk: qcom: camcc-sc8180x: Add missing HW_CTRL GDSC flag To: Val Packett , Bjorn Andersson , Michael Turquette , Stephen Boyd , Vladimir Zapolskiy , Dmitry Baryshkov , Satya Priya Kakitapalli Cc: Konrad Dybcio , Johan Hovold , Manivannan Sadhasivam , Dmitry Baryshkov , Maximilian Luz , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260312112321.370983-1-val@packett.cool> <20260312112321.370983-11-val@packett.cool> <36da7262-0dda-4bb1-b9f2-abd77ef83730@oss.qualcomm.com> <31c68360-97a6-4e23-9d5f-f141abf0790c@packett.cool> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <31c68360-97a6-4e23-9d5f-f141abf0790c@packett.cool> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: _UwtUJllI9JmmSrGvteLzqPbzIq_OWaT X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE2MDA3MSBTYWx0ZWRfX+sB+WqS4OJ5D DMI6A1RugDV84RMZ16ox0Fzzq56K9yff05INlRztzbVqo5tFk602IHookmk+3f6Pdh8S/DQAlPI 0+2zZbD+jLs+h0ZEjVFHFfxx5d2An/AlQ1jdWG8Wp1nOBD4lP06fonyYiFvzkoTd1YtBpfjhEZ+ dboRJME6FKdSLKK9Fq7Z6CUXz52vvwn4H2NASooQpII04pka3NiclBw3xuV7PF+XD4VYwPh10Qo e4kDuydJX/uBLSF+/9BmCO85xcHeDAv8wb12qCBUQ7azaA5YJvoIblwiYhkxKqu1OfqHfvJl90I lQmiHldnWkmCS4YBzuTQynROLq7/klXOYgmSaX13AbUpHNbgJbNFEOmlzgVaB7b3FtPk4mkpja4 LPr+EmUltaA7NdLu5M49LGGJtMu2ruRxI/crH0ZTyH/WQQ0SC6BORzjmkWIJpjWjiLYUrwSAn2b AaB5HOkW6sb9PpJFBuA== X-Proofpoint-ORIG-GUID: _UwtUJllI9JmmSrGvteLzqPbzIq_OWaT X-Authority-Analysis: v=2.4 cv=ZbQQ98VA c=1 sm=1 tr=0 ts=69b7cc63 cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=wZf2C7TumtqOn80vQZ8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-16_03,2026-03-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 adultscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 phishscore=0 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603160071 On 3/14/26 1:13 AM, Val Packett wrote: > > On 3/13/26 7:53 AM, Konrad Dybcio wrote: >> On 3/12/26 12:12 PM, Val Packett wrote: >>> In all other Qualcomm SoC camcc drivers, the BPS and IPE GDSCs use the >>> HW_CTRL flag, but it was missing on SC8180X. >>> >>> Fix by setting it on all applicable GDSC entries. >>> >>> Fixes: 691f3413baa4 ("clk: qcom: camcc-sc8180x: Add SC8180X camera clock controller driver") >>> Signed-off-by: Val Packett >>> --- >>>   drivers/clk/qcom/camcc-sc8180x.c | 6 +++--- >>>   1 file changed, 3 insertions(+), 3 deletions(-) >>> >>> diff --git a/drivers/clk/qcom/camcc-sc8180x.c b/drivers/clk/qcom/camcc-sc8180x.c >>> index cd4c40a81c28..67b2055bd212 100644 >>> --- a/drivers/clk/qcom/camcc-sc8180x.c >>> +++ b/drivers/clk/qcom/camcc-sc8180x.c >>> @@ -2555,7 +2555,7 @@ static struct gdsc bps_gdsc = { >>>       }, >>>       .pwrsts = PWRSTS_OFF_ON, >>>       .parent = &titan_top_gdsc.pd, >>> -    .flags = POLL_CFG_GDSCR, >>> +    .flags = HW_CTRL | POLL_CFG_GDSCR, >> FWIW downstream seems to use HW_MODE at runtime and SW_MODE+collapse on >> suspend for both BPS and IPE, so perhaps HW_CTRL_TRIGGER (and a patch to >> the driver) would be better suited > > Hmm what exactly would that "patch to the driver" be? Not sure I understood that part… There's now a dev_pm_genpd_set_hwmode() that on GDSCs translates to toggling the HW_CTRL bit in the register at runtime Konrad