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Mon, 21 Sep 2026 06:47:08 -0700 (PDT) X-Received: by 2002:a17:903:2f0f:b0:2d8:d4d0:7930 with SMTP id d9443c01a7336-2ddb1b98b90mr155543555ad.20.1789998428217; Mon, 21 Sep 2026 06:47:08 -0700 (PDT) Received: from [192.168.29.146] ([49.43.232.81]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ddc18032d5sm34621395ad.83.2026.09.21.06.47.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 21 Sep 2026 06:47:07 -0700 (PDT) Message-ID: <7b5bec8a-87ed-4363-ac62-3e14f7619f13@oss.qualcomm.com> Date: Mon, 21 Sep 2026 19:17:00 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/5] dt-bindings: PCI: qcom,shikra-pcie: Document the Shikra PCIe Controller To: Krzysztof Kozlowski Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Andersson , Chaitanya Chundru , Bartosz Golaszewski , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org References: <20260831-shikra-upstream-v2-0-406661d75afa@oss.qualcomm.com> <20260831-shikra-upstream-v2-2-406661d75afa@oss.qualcomm.com> <20260901-silent-pearl-shrew-c63a16@quoll> Content-Language: en-US From: Sushrut Shree Trivedi In-Reply-To: <20260901-silent-pearl-shrew-c63a16@quoll> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=SJLXx+vH c=1 sm=1 tr=0 ts=6ab13562 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=gjxls31er4aXgMEaaoPcOA==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=tLOCWTNIkaiYH31-AwAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: LT0oxDSFXZSJPO-Ko_C0NBfOAhjOOQwq X-Proofpoint-ORIG-GUID: LT0oxDSFXZSJPO-Ko_C0NBfOAhjOOQwq X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIxMDIwMCBTYWx0ZWRfX6nVKDU4oM9c+ 7FF1fIrUu3yt2D7kVogn4Pd/WJ98bsNS32WWyZXgfkkzvBo/AwGRpX26Evjy9a2PhdfblNK58U0 Yq4ucHnwi9GW1edHn3TgTq7CA0bl0f4= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIxMDIwMCBTYWx0ZWRfX9lg8EhC9jtD0 0hDs3xrjm4hkifmDZ1lF+UrdqC0XcXpMAxFmv55hkjtmXxc20d0nVPzmeiNt11dN9nKYsQjSFWq jv+hG7gVRGGWoosI7LyFW0EuLb1CLWtA4QTjuVPPXypKZEZvwYIQdij+NN+sHZI2BtISJ+d74S8 fdevaHQ6z5zn2cv6HmVo6l1je7qbcItNmbz7l7e/XmCICs8BUi6Z22G8cO6ISi0fdVxw8l4vqL7 MsLF32IeIVK5aox3j0J4+qoBwCAU9tVDlL/W9YkrbQGJ8cEm1rpjzt4wwMAF5fIDNksVMlfTD0W YY3T0rrzp/FUYY0/eJAEmNVYPa60KD/oXG+/ZYhYRJs1MXaqkHROU/DhmtvV+CKE8xSGovUUA1V Py1AdlKecMOaTKJWwNEDHmbIMHpeJvjli/8/CnAPVZDwTbvtgFol0wn9qfc6dsMc0eSsmVpDSAJ K79YchSMTGWe22MXl/w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-21_04,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 malwarescore=0 adultscore=0 clxscore=1015 bulkscore=0 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609210200 On 9/1/2026 2:12 PM, Krzysztof Kozlowski wrote: > On Mon, Aug 31, 2026 at 12:56:02PM +0530, Sushrut Shree Trivedi wrote: >> Add a dedicated schema for the PCIe controller found on the Shikra >> platform. >> >> Shikra controller supports upto PCIe Gen3 but the PHY is >> only capable of Gen2, hence the max link speed is limited >> to Gen2 to avoid link-up failures. >> >> Signed-off-by: Sushrut Shree Trivedi >> --- >> .../devicetree/bindings/pci/qcom,shikra-pcie.yaml | 218 +++++++++++++++++++++ >> 1 file changed, 218 insertions(+) >> > What is the difference in the binding against Eliza? IOW, why does this > need a separate file unlike Eliza? Shikra does not have the Config NoC AXI clock unlike sm8550 / eliza. Apart from that, minItems for reg  and interrupts need to be updated. I actually didn't see any bindings with a clock constraint added for only a single compatible. Do you suggest constraining shikra clock-names and other properties under an if block inside sm8550 binding itself ? > > ... > >> + reset-names = "pci"; >> + >> + power-domains = <&gcc GCC_PCIE_GDSC>; >> + >> + max-link-speed = <2>; >> + >> + operating-points-v2 = <&pcie_opp_table>; >> + >> + pcie_opp_table: opp-table { >> + compatible = "operating-points-v2"; > Are you sure dt-check-style does not complain? ACK'd > >> + >> + /* GEN 1 x1 */ >> + opp-2500000 { >> + opp-hz = /bits/ 64 <2500000>; >> + required-opps = <&rpmpd_opp_low_svs>; >> + opp-peak-kBps = <250000 1>; >> + opp-level = <1>; >> + }; >> + > Best regards, > Krzysztof