From: Damien Le Moal <damien.lemoal@opensource.wdc.com>
To: Paul Menzel <pmenzel@molgen.mpg.de>
Cc: linux-ide@vger.kernel.org,
Dmitry Torokhov <dmitry.torokhov@gmail.com>,
Guenter Roeck <groeck@chromium.org>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 3/3] ahci: AMD A85 FCH (Hudson D4): Skip 200 ms debounce delay in `sata_link_resume()`
Date: Fri, 31 Dec 2021 09:52:04 +0900 [thread overview]
Message-ID: <7b64d1c3-f798-d64b-9ee3-9669d98f4e28@opensource.wdc.com> (raw)
In-Reply-To: <19f6cd93-9bd7-60dc-4471-18022bcf456c@molgen.mpg.de>
On 12/30/21 20:08, Paul Menzel wrote:
>>> board_ahci_nomsi,
>>> board_ahci_noncq,
>>> board_ahci_nosntf,
>>> @@ -141,6 +142,13 @@ static const struct ata_port_info ahci_port_info[] = {
>>> .udma_mask = ATA_UDMA6,
>>> .port_ops = &ahci_ops,
>>> },
>>> + [board_ahci_nodbdelay] = {
>>> + .flags = AHCI_FLAG_COMMON,
>>> + .link_flags = ATA_LFLAG_NO_DB_DELAY,
>>> + .pio_mask = ATA_PIO4,
>>> + .udma_mask = ATA_UDMA6,
>>> + .port_ops = &ahci_ops,
>>> + },
>>> [board_ahci_nomsi] = {
>>> AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
>>> .flags = AHCI_FLAG_COMMON,
>>> @@ -437,6 +445,7 @@ static const struct pci_device_id ahci_pci_tbl[] = {
>>> board_ahci_al },
>>> /* AMD */
>>> { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE), board_ahci },
>>> + { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_AHCI), board_ahci_nodbdelay },
>>
>> Patch 1 introduces this macro in pci_ids.h, but it is used only here. So
>> to keep with the current style in this structure, drop the macro (so
>> drop patch 1).
>
> I wait for your answer of the second patch, and then I am going to sent v4.
Let's use the numeric value. No macro definition needed.
>
>>> { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
>>> { PCI_VDEVICE(AMD, 0x7901), board_ahci_mobile }, /* AMD Green Sardine */
>>> /* AMD is using RAID class only for ahci controllers */
>
> Do you have a AHCI device at hand, where you could also test if
> everything works fine without the delay?
Unfortunately, I do not have any board with this adapter.
Cheers.
--
Damien Le Moal
Western Digital Research
next prev parent reply other threads:[~2021-12-31 0:52 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-29 16:11 [PATCH v3 1/3] PCI: Add device code for AMD FCH SATA Controller in AHCI mode Paul Menzel
2021-12-29 16:11 ` [PATCH v3 2/3] ahci: Use macro PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE Paul Menzel
2021-12-30 2:13 ` Damien Le Moal
2021-12-30 11:01 ` Paul Menzel
2021-12-31 0:50 ` Damien Le Moal
2021-12-30 13:35 ` Hannes Reinecke
2021-12-29 16:11 ` [PATCH v3 3/3] ahci: AMD A85 FCH (Hudson D4): Skip 200 ms debounce delay in `sata_link_resume()` Paul Menzel
2021-12-30 2:19 ` Damien Le Moal
2021-12-30 11:08 ` Paul Menzel
2021-12-31 0:52 ` Damien Le Moal [this message]
2021-12-31 7:08 ` Paul Menzel
2022-01-04 8:36 ` Damien Le Moal
2022-01-04 8:49 ` Paul Menzel
2022-01-04 9:08 ` Damien Le Moal
2022-01-04 11:34 ` ata: For what PHY was debounce delay introduced? (was: [PATCH v3 3/3] ahci: AMD A85 FCH (Hudson D4): Skip 200 ms debounce delay in `sata_link_resume()`) Paul Menzel
[not found] ` <CAHy7=M10exWuVJtDVo+w36YKadY533GttzwrKxPnotHf8-JQnw@mail.gmail.com>
2022-01-07 21:30 ` Tejun Heo
2022-01-04 6:04 ` [PATCH v3 3/3] ahci: AMD A85 FCH (Hudson D4): Skip 200 ms debounce delay in `sata_link_resume()` Dmitry Torokhov
2021-12-30 19:21 ` [PATCH v3 1/3] PCI: Add device code for AMD FCH SATA Controller in AHCI mode Sergei Shtylyov
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