From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E991C433E2 for ; Mon, 7 Sep 2020 16:09:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E664A2087D for ; Mon, 7 Sep 2020 16:09:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730314AbgIGQJx (ORCPT ); Mon, 7 Sep 2020 12:09:53 -0400 Received: from mx.socionext.com ([202.248.49.38]:4579 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730295AbgIGQJ1 (ORCPT ); Mon, 7 Sep 2020 12:09:27 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 08 Sep 2020 01:09:24 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 84AF060060; Tue, 8 Sep 2020 01:09:24 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Tue, 8 Sep 2020 01:09:24 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id EA8C01A0509; Tue, 8 Sep 2020 01:09:23 +0900 (JST) Received: from [10.212.1.10] (unknown [10.212.1.10]) by yuzu.css.socionext.com (Postfix) with ESMTP id 299A91205FF; Tue, 8 Sep 2020 01:09:23 +0900 (JST) Subject: Re: [PATCH v6 5/6] PCI: uniphier: Add iATU register support To: Rob Herring Cc: Lorenzo Pieralisi , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , Masahiro Yamada , Marc Zyngier , PCI , devicetree@vger.kernel.org, "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , "linux-kernel@vger.kernel.org" , Masami Hiramatsu , Jassi Brar References: <1596795922-705-1-git-send-email-hayashi.kunihiko@socionext.com> <1596795922-705-6-git-send-email-hayashi.kunihiko@socionext.com> From: Kunihiko Hayashi Message-ID: <7b6ae470-23c1-735c-08ca-67dd644d7f23@socionext.com> Date: Tue, 8 Sep 2020 01:09:22 +0900 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Rob, On 2020/09/04 7:12, Rob Herring wrote: > On Fri, Aug 21, 2020 at 1:05 AM Kunihiko Hayashi > wrote: >> >> On 2020/08/18 1:48, Rob Herring wrote: >>> On Fri, Aug 7, 2020 at 4:25 AM Kunihiko Hayashi >>> wrote: >>>> >>>> This gets iATU register area from reg property. In Synopsys DWC version >>>> 4.80 or later, since iATU register area is separated from core register >>>> area, this area is necessary to get from DT independently. >>>> >>>> Signed-off-by: Kunihiko Hayashi >>>> --- >>>> drivers/pci/controller/dwc/pcie-uniphier.c | 5 +++++ >>>> 1 file changed, 5 insertions(+) >>>> >>>> diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c >>>> index 55a7166..93ef608 100644 >>>> --- a/drivers/pci/controller/dwc/pcie-uniphier.c >>>> +++ b/drivers/pci/controller/dwc/pcie-uniphier.c >>>> @@ -471,6 +471,11 @@ static int uniphier_pcie_probe(struct platform_device *pdev) >>>> if (IS_ERR(priv->pci.dbi_base)) >>>> return PTR_ERR(priv->pci.dbi_base); >>>> >>>> + priv->pci.atu_base = >>>> + devm_platform_ioremap_resource_byname(pdev, "atu"); >>>> + if (IS_ERR(priv->pci.atu_base)) >>>> + priv->pci.atu_base = NULL; >>> >>> Keystone has the same 'atu' resource setup. Please move its code to >>> the DW core and use that. >> >> There are some platforms that pci.atu_base is set by other way. >> The 'atu' code shouldn't be conflicted with the following existing code. > > No, it's not a conflict but needless duplication. I see. >> drivers/pci/controller/dwc/pci-keystone.c: atu_base = devm_platform_ioremap_resource_byname(pdev, "atu"); >> drivers/pci/controller/dwc/pci-keystone.c: pci->atu_base = atu_base; >> drivers/pci/controller/dwc/pcie-designware.c: pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; >> drivers/pci/controller/dwc/pcie-intel-gw.c: pci->atu_base = pci->dbi_base + data->pcie_atu_offset; > > This one should have had an 'atu' region in DT. > >> drivers/pci/controller/dwc/pcie-tegra194.c: pci->atu_base = devm_ioremap_resource(dev, atu_dma_res); > > Unfortunately, a different name was used. That is the mess which is > the DW PCI controller. Okay, this has already set atu_base, so ignore it for this patch. >> >> So I'm not sure where to move the code in the DW core. >> Is there any idea? > > You just need this and then remove the keystone code: > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c > b/drivers/pci/controller/dwc/pcie-designware.c > index b723e0cc41fb..680084467447 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -556,6 +556,8 @@ void dw_pcie_setup(struct dw_pcie *pci) > dw_pcie_iatu_unroll_enabled(pci))) { > pci->iatu_unroll_enabled = true; > if (!pci->atu_base) > + pci->atu_base = > devm_platform_ioremap_resource_byname(pdev, "atu"); > + if (IS_ERR(pci->atu_base)) > pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; > } > dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? > I've got it. I think I need to add a bit of code to this though, I'll try to apply this and remove the duplicate code. I'll separate this from other PER/AER patches and send new series. Thank you, --- Best Regards Kunihiko Hayashi