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Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH] accel/amdxdna: Check interrupt register before mailbox_rx_worker exits Content-Language: en-US To: Jacek Lawrynowicz , , , , CC: , , , , References: <20250225172616.3804796-1-lizhi.hou@amd.com> <8c8fbd0a-7c5f-49e7-b02d-031e8b712883@linux.intel.com> From: Lizhi Hou In-Reply-To: <8c8fbd0a-7c5f-49e7-b02d-031e8b712883@linux.intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB05.amd.com: lizhi.hou@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231C:EE_|LV8PR12MB9232:EE_ X-MS-Office365-Filtering-Correlation-Id: 0eea61c3-457f-427c-d0ca-08dd56806129 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?B?ZkErS2lWRU5JZ08rZDhhTDd2K25BUDR6N0lwdVZuRTI4MmZYODNKa0daZ0U4?= =?utf-8?B?VlRqSnFTeFN1VFVOOU4zK0JKdWI5aFhxVWIzN1JGODA2ejFTYnQrZnFMdFZH?= =?utf-8?B?Z01iN0VtSlV6dUdvdmliMVRGdDJwbGsvOXhZTzM1ZTZlZWRjQTlDaExqVEYw?= =?utf-8?B?cis3QzJHWjJmZkp0SUkvOG9iWEpzb0xZSjZzenM5aVRVZTlHUnpkSXloRUU4?= =?utf-8?B?NnllbXRSc0RJMnVWdEVkVTVtN0NnWEtKcmw1SkRLS3FGclE0QlpxYXp4ell6?= =?utf-8?B?WG1QRi9KQXNWZWJ2alJ2WGJ3aE1Jd3g0RmRleUNaM2lYNmhiTmhBSldrUklv?= =?utf-8?B?WEw4V2FaY0pVYjNWcjA5MkExT1ZBZ040OFE2QUo4SzJvRHQ4YTd6MTZKaXpt?= =?utf-8?B?c01xUnVIRFpyRVVNZmFSUENHdUlKcEE0ckMxamFPUDRZb1R1dkdHTVcvVEdJ?= =?utf-8?B?QVlBckh3a3FMektrWHc3VlV5bzlzc0pIK211TzdlTTRxU090RTN6WWZrNlEz?= =?utf-8?B?dnBEZGNieC8yMzZYVXRWQWlpazhiMXJ6cm1EaVRVYThGcUNrL3BEQWhZVlZR?= =?utf-8?B?eHpxd3NsK0VWYjBzd3RGKzFHTlBMUDZqUEVpbTBENFRzdDNJRDVmYUt0TGI2?= =?utf-8?B?ZjNSNmpQQ2xUZ1VNdnMwUjdSdDI1cFZMSVZpR1FKdWVScmM0MGh5bTlDc1Ix?= =?utf-8?B?R1JWRlhTM1FKYmI2UVpGc1ZWQXRmWTZPNm9VQ3VwY241UGp6VlMzclZqVnBB?= =?utf-8?B?QmR0UHYvdUZhS09ySmFWQTRud2tCbnlLcjVLT1VpUEF4Rk9iRVZYeGhLYU9k?= =?utf-8?B?MUNwVTd6aDF6enVYbllRMEx5TnhzbTRhdDBFVkwzT3NBQWFwcmhqTmJSYkF4?= =?utf-8?B?QTYyZ3Iwa3F1dm9DNjdiQkRxcXBJdUQ1VTAyR1M1WDBqVG51dllvczgraEV4?= =?utf-8?B?R3UxdmhXUzNmVWZWc3dvRHJTV0J2cUhDVzd3UmNLUUszZGhvTXhVNURNdDRm?= =?utf-8?B?MzBlTFVUR1VzVVozeklkUlZ3bmFNdjNGU2tzKzhwSEVLU1Y0TkFnOHdPdy93?= =?utf-8?B?RUZwVVlKN2JUQktndSsvczMwcTFMWFF0MjE5QThIZ1VLRm1YR3h0MXlwak5J?= =?utf-8?B?QVlhL3BhZ25XM0ZSWE5HZzdUSDc2OS9qdVZTRU1GdUpVNWNwSnJPRXF0T0RU?= =?utf-8?B?SkZnMXVvdHpPNmxKdVliMkEyRW0zdnovVkdBNW14anVJVU5IQk9KUTZaRXpD?= =?utf-8?B?VThMSHBQcm9ka293OW10cEhTS29yQkxhTHlLMXJ5Rk1Pb2xoTVhsWFdWYWRW?= =?utf-8?B?MEpubEg1NEpuem9PSWtKbG5aeWVsMGdUcFFmdXI4U3FiVUFQTFBFVXFRMVVn?= =?utf-8?B?MmNQQ0VRU1R0NGZHR1BLeFpOY2xPYWFnbk9hblNaWkY3SUpGaWdOaHFMMmlD?= =?utf-8?B?K21GeGlHZ1B4VlFDZzlSenRncDhjYVE5Y25sbFJRQ2k1aDd6dGE0SDVXaTlV?= =?utf-8?B?T0JQYUpnbGRJY1RoTFNaU0t0dzNOc3ZMRmxxbzloamVCeEROLzBrcnUvMGY2?= =?utf-8?B?U3pxcW1YcnNlWEI4OS9QTVRwekUzc21NTEN1VXhQVjgwM0Qyc08wVmF0R25s?= =?utf-8?B?RHZ1SEJDSEliMWFicTIzejJrQXBFZlg1aXZXamJ5cC96QXZ5bmM3d1duUjRa?= =?utf-8?B?UTFTMXloUjRkWmZ6T1dnQzB4NncxNEY4U094Wndmek9JaXAyU05FekpWREtC?= =?utf-8?B?WkRHbnVhcklHUER1dktYN0lQUk5USmJHQmQ3QWp4ZFNkd216clNZVElRcUZy?= =?utf-8?B?NlZ1TUpoanJwVmoyL0ZjMzNDRG9MTkRJeW9zNDhocVU4NmttTzJMaU53SER4?= =?utf-8?B?UWljVE1EbmF5YTJRT2oydmszbS8xVUdjNDIyV3VES203QmY3d0QyVnMyeCtv?= =?utf-8?B?SE9jQnJXcGppaXo5SlRtclI0Z1ZXUEZlaEdjYk53NUppd3djRzZhNlBFZnla?= =?utf-8?B?MmlKYko0dDFnPT0=?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2025 16:12:34.0848 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0eea61c3-457f-427c-d0ca-08dd56806129 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9232 On 2/26/25 01:30, Jacek Lawrynowicz wrote: > Hi, > > On 2/25/2025 6:26 PM, Lizhi Hou wrote: >> There is a timeout failure been found during stress tests. If the firmware >> generates a mailbox response right after driver clears the mailbox channel >> interrupt register, the hardware will not generate an interrupt for the >> response. This causes the unexpected mailbox command timeout. >> >> To handle this failure, driver checks the interrupt register before >> exiting mailbox_rx_worker(). If there is a new response, driver goes back >> to process it. >> >> Signed-off-by: Lizhi Hou >> --- >> drivers/accel/amdxdna/amdxdna_mailbox.c | 18 +++++++++++++++--- >> 1 file changed, 15 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/accel/amdxdna/amdxdna_mailbox.c b/drivers/accel/amdxdna/amdxdna_mailbox.c >> index de7bf0fb4594..efe6cbc44d14 100644 >> --- a/drivers/accel/amdxdna/amdxdna_mailbox.c >> +++ b/drivers/accel/amdxdna/amdxdna_mailbox.c >> @@ -348,8 +348,6 @@ static irqreturn_t mailbox_irq_handler(int irq, void *p) >> trace_mbox_irq_handle(MAILBOX_NAME, irq); >> /* Schedule a rx_work to call the callback functions */ >> queue_work(mb_chann->work_q, &mb_chann->rx_work); >> - /* Clear IOHUB register */ >> - mailbox_reg_write(mb_chann, mb_chann->iohub_int_addr, 0); >> >> return IRQ_HANDLED; >> } >> @@ -357,6 +355,7 @@ static irqreturn_t mailbox_irq_handler(int irq, void *p) >> static void mailbox_rx_worker(struct work_struct *rx_work) >> { >> struct mailbox_channel *mb_chann; >> + u32 iohub; > There is no need for this variable. Just use if (mailbox_reg_read()). Sure. Will fix this. > >> int ret; >> >> mb_chann = container_of(rx_work, struct mailbox_channel, rx_work); >> @@ -366,6 +365,9 @@ static void mailbox_rx_worker(struct work_struct *rx_work) >> return; >> } >> >> +again: >> + mailbox_reg_write(mb_chann, mb_chann->iohub_int_addr, 0); >> + >> while (1) { >> /* >> * If return is 0, keep consuming next message, until there is >> @@ -380,9 +382,19 @@ static void mailbox_rx_worker(struct work_struct *rx_work) >> MB_ERR(mb_chann, "Unexpected ret %d, disable irq", ret); >> WRITE_ONCE(mb_chann->bad_state, true); >> disable_irq(mb_chann->msix_irq); >> - break; >> + return; > disable_irq() should not be called here. It will be called for the second time in xdna_mailbox_stop_channel() and enable/disable calls should be balanced. Agree. I will remove disable_irg(). Thanks, Lizhi > >> } >> } >> + >> + /* >> + * The hardware will not generate interrupt if firmware creates a new >> + * response right after driver clears interrupt register. Check >> + * the interrupt register to make sure there is not any new response >> + * before exiting. >> + */ >> + iohub = mailbox_reg_read(mb_chann, mb_chann->iohub_int_addr); >> + if (iohub) >> + goto again; >> } >> >> int xdna_mailbox_send_msg(struct mailbox_channel *mb_chann, > Regards, > Jacek