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Thu, 12 Nov 2026 04:38:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1794487104; bh=GXDArifiTXzGS/TEyKUeQy694OV8tzZyyHhxUDTufKU=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=G92ewwS69xI/sQnwPuFxDuaGeeicD5gWXRAQcqnYkeOnE+1AhuhQD+T9u+2gEnSvA 8Tz0b5fy8Nanp500jVMIfPIBqybgWOu28wUx9eUNS6BsJB8hlKLfKfowurrVqb8yg0 gegWtANRaNOjC5bAe0P7rnTdXxQKCb9wTnu50CiQ= Message-ID: <7b92f7c8-1543-447e-8ef3-aba608141699@arm.com> Date: Thu, 12 Nov 2026 13:38:13 +0100 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v10 07/22] arm64: Initialize POR_EL1 register on cpu_resume() To: Yeoreum Yun , Mark Brown Cc: linux-hardening@vger.kernel.org, Andrew Morton , Ard Biesheuvel , Andy Lutomirski , Catalin Marinas , Dave Hansen , "David Hildenbrand (Arm)" , Jann Horn , Jeff Xu , Joey Gouly , Kees Cook , Linu Cherian , Linus Walleij , Marc Zyngier , Matthew Wilcox , Maxwell Bland , "Mike Rapoport (IBM)" , Peter Zijlstra , Pierre Langlois , =?UTF-8?Q?Pierre-Cl=C3=A9ment_Tosi?= , Quentin Perret , Rick Edgecombe , Ryan Roberts , Vlastimil Babka , Will Deacon , Yang Shi , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, x86@kernel.org, Ira Weiny , Lorenzo Stoakes , Thomas Gleixner References: <20261109-kpkeys-v10-0-aa6c4d9603bc@arm.com> <20261109-kpkeys-v10-7-aa6c4d9603bc@arm.com> From: Kevin Brodsky Content-Language: en-GB In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 10/11/2026 17:36, Yeoreum Yun wrote: > On Tue, Nov 10, 2026 at 03:53:30PM +0000, Mark Brown wrote: >> On Mon, Nov 09, 2026 at 03:58:32PM +0000, Kevin Brodsky wrote: >>> From: Yeoreum Yun >>> >>> The POR_EL1 register is reset to an unknown value after cpu_suspend(). >>> Since POR_EL1 always holds POR_EL1_INIT when entering cpu_suspend(), >>> initialize POR_EL1 with POR_EL1_INIT before cpu_do_resume(). >>>> +#ifdef CONFIG_ARM64_POE >>> +alternative_if_not ARM64_HAS_S1POE >>> + b .Lskip_por_set >>> +alternative_else_nop_endif >>> + mov_q x2, POR_EL1_INIT >>> + msr_s SYS_POR_EL1, x2 >>> + /* isb can be skipped since cpu_do_resume() will do it. */ >>> +.Lskip_por_set: >>> +#endif /* CONFIG_ARM64_POE */ >> cpu_do_resume() will update TCR2_EL1 to enable POE again, a sufficiently >> unhelpful implementation could potentially decide to do that before this >> POR_EL1 value takes effect AFAICT given that there's no barriers. > Thanks. seems required to isb() after initialising SYS_POR_EL1. Agreed (as Sashiko reported as well). Presumably that means we also need an ISB after writing to POR_EL1 in cpu_enable_poe(), as that's basically the same situation. - Kevin