From: neil.armstrong@linaro.org
To: Hsieh Hung-En <hungen3108@gmail.com>,
dianders@chromium.org, jesszhan0024@gmail.com
Cc: jagan@amarulasolutions.com, osama.abdelkader@gmail.com,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
maarten.lankhorst@linux.intel.com, mripard@kernel.org,
tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch
Subject: Re: [PATCH v2 4/5] drm/panel: raydium-rm68200: Use mipi_dsi_*_multi() functions
Date: Mon, 2 Nov 2026 14:02:36 +0100 [thread overview]
Message-ID: <7ba2f6b7-a9b8-4558-b62e-84261f1c3e9b@linaro.org> (raw)
In-Reply-To: <20261102043215.990351-5-hungen3108@gmail.com>
On 11/2/26 05:32, Hsieh Hung-En wrote:
> Replace the deprecated MIPI DSI DCS helpers and custom DCS write
> wrappers with their multi-context equivalents.
>
> Preserve individual DCS transactions for registers that do not support
> auto-increment. Share the multi-context with rm68200_init_sequence()
> so that initialization failures stop subsequent DCS transfers and
> cause prepare() to fail instead of only being logged. Errors are
> handled by the cleanup path in prepare().
>
> Use mipi_dsi_msleep() to skip delays after a failed command. In
> unprepare(), clear accum_err between commands so that ENTER_SLEEP_MODE
> is still attempted if SET_DISPLAY_OFF fails.
>
> The new helpers log failures at error level. Initialization write
> errors are no longer rate-limited.
>
> Signed-off-by: Hsieh Hung-En <hungen3108@gmail.com>
> ---
>
> Notes:
> Changes in v2:
> - Merge v1 patches 2/3 and 3/3, as suggested by Doug.
> - Route initialization and DCS command failures through the prepare()
> error cleanup path introduced earlier in this series.
> - Drop Doug's Reviewed-by tag from v1 3/3 because the patches were
> merged and the error handling was reworked.
>
> Validation:
> - Mechanically compared all 58 initialization calls against v1.
> Command addresses, payloads, and ordering are unchanged.
> - Verified the expansion of dcs_write_cmd_seq() in v1 using
> preprocessed output, confirming that each register address is
> written in a separate DCS transaction. The macro is unchanged
> from v1.
>
> The uppercase hexadecimal literals are retained in this patch.
> Their formatting will be addressed separately in the next patch.
>
> drivers/gpu/drm/panel/panel-raydium-rm68200.c | 208 ++++++++----------
> 1 file changed, 91 insertions(+), 117 deletions(-)
>
> diff --git a/drivers/gpu/drm/panel/panel-raydium-rm68200.c b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
> index 3a59eb00274d..8ce89f09540c 100644
> --- a/drivers/gpu/drm/panel/panel-raydium-rm68200.c
> +++ b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
> @@ -98,149 +98,123 @@ static inline struct rm68200 *panel_to_rm68200(struct drm_panel *panel)
> return container_of(panel, struct rm68200, panel);
> }
>
> -static void rm68200_dcs_write_buf(struct rm68200 *ctx, const void *data,
> - size_t len)
> -{
> - struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
> - int err;
> -
> - err = mipi_dsi_dcs_write_buffer(dsi, data, len);
> - if (err < 0)
> - dev_err_ratelimited(ctx->dev, "MIPI DSI DCS write buffer failed: %d\n", err);
> -}
> -
> -static void rm68200_dcs_write_cmd(struct rm68200 *ctx, u8 cmd, u8 value)
> -{
> - struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
> - int err;
> -
> - err = mipi_dsi_dcs_write(dsi, cmd, &value, 1);
> - if (err < 0)
> - dev_err_ratelimited(ctx->dev, "MIPI DSI DCS write failed: %d\n", err);
> -}
> -
> -#define dcs_write_seq(ctx, seq...) \
> -({ \
> - static const u8 d[] = { seq }; \
> - \
> - rm68200_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \
> -})
> -
> /*
> * This panel is not able to auto-increment all cmd addresses so for some of
> * them, we need to send them one by one...
> + *
> + * Use arr instead of d to avoid shadowing the local d[] declared by
> + * mipi_dsi_dcs_write_var_seq_multi().
> */
> -#define dcs_write_cmd_seq(ctx, cmd, seq...) \
> -({ \
> - static const u8 d[] = { seq }; \
> - unsigned int i; \
> - \
> - for (i = 0; i < ARRAY_SIZE(d) ; i++) \
> - rm68200_dcs_write_cmd(ctx, cmd + i, d[i]); \
> -})
> -
> -static void rm68200_init_sequence(struct rm68200 *ctx)
> +#define dcs_write_cmd_seq(dsi_ctx, cmd, seq...) \
> + do { \
> + static const u8 arr[] = { seq }; \
> + unsigned int i; \
> + \
> + for (i = 0; i < ARRAY_SIZE(arr); i++) \
> + mipi_dsi_dcs_write_var_seq_multi(dsi_ctx, \
> + (cmd) + i, arr[i]); \
> + } while (0)
> +
> +static void rm68200_init_sequence(struct mipi_dsi_multi_context *dsi_ctx)
> {
> /* Enter CMD2 with page 0 */
> - dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P0);
> - dcs_write_cmd_seq(ctx, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00);
> - dcs_write_seq(ctx, MCS_BT2CTR, 0xE5);
> - dcs_write_seq(ctx, MCS_SETAVDD, 0x0A);
> - dcs_write_seq(ctx, MCS_SETAVEE, 0x0A);
> - dcs_write_seq(ctx, MCS_SGOPCTR, 0x52);
> - dcs_write_seq(ctx, MCS_BT3CTR, 0x53);
> - dcs_write_seq(ctx, MCS_BT4CTR, 0x5A);
> - dcs_write_seq(ctx, MCS_INVCTR, 0x00);
> - dcs_write_seq(ctx, MCS_STBCTR, 0x0A);
> - dcs_write_seq(ctx, MCS_SDCTR, 0x06);
> - dcs_write_seq(ctx, MCS_VCMCTR, 0x56);
> - dcs_write_seq(ctx, MCS_SETVGN, 0xA0, 0x00);
> - dcs_write_seq(ctx, MCS_SETVGP, 0xA0, 0x00);
> - dcs_write_seq(ctx, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */
> -
> - dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P2);
> - dcs_write_seq(ctx, GOA_VSTV1, 0x05);
> - dcs_write_seq(ctx, 0x02, 0x0B);
> - dcs_write_seq(ctx, 0x03, 0x0F);
> - dcs_write_seq(ctx, 0x04, 0x7D, 0x00, 0x50);
> - dcs_write_cmd_seq(ctx, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00,
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, MCS_CMD2_P0);
> + dcs_write_cmd_seq(dsi_ctx, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BT2CTR, 0xE5);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETAVDD, 0x0A);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETAVEE, 0x0A);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SGOPCTR, 0x52);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BT3CTR, 0x53);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BT4CTR, 0x5A);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_INVCTR, 0x00);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_STBCTR, 0x0A);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SDCTR, 0x06);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_VCMCTR, 0x56);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETVGN, 0xA0, 0x00);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETVGP, 0xA0, 0x00);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */
> +
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, MCS_CMD2_P2);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_VSTV1, 0x05);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x02, 0x0B);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x03, 0x0F);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x04, 0x7D, 0x00, 0x50);
> + dcs_write_cmd_seq(dsi_ctx, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00,
> 0x50);
> - dcs_write_cmd_seq(ctx, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D,
> + dcs_write_cmd_seq(dsi_ctx, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D,
> 0x00, 0x85, 0x08);
> - dcs_write_cmd_seq(ctx, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D,
> + dcs_write_cmd_seq(dsi_ctx, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D,
> 0x00, 0x85, 0x08);
> - dcs_write_seq(ctx, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> - 0x00, 0x00, 0x00, 0x00);
> - dcs_write_cmd_seq(ctx, GOA_BICLK1, 0x07, 0x08);
> - dcs_write_seq(ctx, 0x2D, 0x01);
> - dcs_write_seq(ctx, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D,
> - 0x00);
> - dcs_write_cmd_seq(ctx, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00);
> - dcs_write_seq(ctx, 0x3D, 0x40);
> - dcs_write_seq(ctx, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00);
> - dcs_write_seq(ctx, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> - 0x00, 0x00, 0x00, 0x00, 0x00);
> - dcs_write_seq(ctx, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> - 0x00, 0x00);
> - dcs_write_seq(ctx, 0x58, 0x00, 0x00, 0x00);
> - dcs_write_seq(ctx, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00);
> - dcs_write_seq(ctx, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
> - dcs_write_seq(ctx, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00);
> - dcs_write_seq(ctx, MCS_GOA_GPO2, 0x00, 0x20, 0x00);
> - dcs_write_seq(ctx, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
> - 0x00, 0x00);
> - dcs_write_seq(ctx, MCS_GOA_CLK_GALLON, 0x00, 0x00);
> - dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10,
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00);
> + dcs_write_cmd_seq(dsi_ctx, GOA_BICLK1, 0x07, 0x08);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x2D, 0x01);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D,
> + 0x00);
> + dcs_write_cmd_seq(dsi_ctx, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x3D, 0x40);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x58, 0x00, 0x00, 0x00);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_GOA_GPO2, 0x00, 0x20, 0x00);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
> + 0x00, 0x00);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_GOA_CLK_GALLON, 0x00, 0x00);
> + dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10,
> 0x16, 0x12, 0x08, 0x3F);
> - dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C,
> + dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C,
> 0x0A, 0x0E, 0x3F, 0x3F, 0x00);
> - dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F,
> + dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F,
> 0x05, 0x01, 0x3F, 0x3F, 0x0F);
> - dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F,
> + dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F,
> 0x3F);
> - dcs_write_cmd_seq(ctx, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15);
> - dcs_write_cmd_seq(ctx, 0xA9, 0x07, 0x03, 0x3F);
> - dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13,
> + dcs_write_cmd_seq(dsi_ctx, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15);
> + dcs_write_cmd_seq(dsi_ctx, 0xA9, 0x07, 0x03, 0x3F);
> + dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13,
> 0x15, 0x11, 0x0F, 0x3F);
> - dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B,
> + dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B,
> 0x0D, 0x09, 0x3F, 0x3F, 0x07);
> - dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F,
> + dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F,
> 0x02, 0x06, 0x3F, 0x3F, 0x08);
> - dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F,
> + dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F,
> 0x3F, 0x3F, 0x0E, 0x10, 0x14);
> - dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F);
> - dcs_write_seq(ctx, 0xDC, 0x02);
> - dcs_write_seq(ctx, 0xDE, 0x12);
> + dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xDC, 0x02);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xDE, 0x12);
>
> - dcs_write_seq(ctx, MCS_CMD_MODE_SW, 0x0E); /* No documentation */
> - dcs_write_seq(ctx, 0x01, 0x75);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, 0x0E); /* No documentation */
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x01, 0x75);
>
> - dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P3);
> - dcs_write_cmd_seq(ctx, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06,
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, MCS_CMD2_P3);
> + dcs_write_cmd_seq(dsi_ctx, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06,
> 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
> 0x12, 0x0C, 0x00);
> - dcs_write_cmd_seq(ctx, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06,
> + dcs_write_cmd_seq(dsi_ctx, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06,
> 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
> 0x12, 0x0C, 0x00);
>
> /* Exit CMD2 */
> - dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD1_UCS);
> + mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, MCS_CMD1_UCS);
> }
>
> static int rm68200_unprepare(struct drm_panel *panel)
> {
> struct rm68200 *ctx = panel_to_rm68200(panel);
> struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
> - int ret;
> + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
>
> - ret = mipi_dsi_dcs_set_display_off(dsi);
> - if (ret)
> - dev_warn(panel->dev, "failed to set display off: %d\n", ret);
> + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
>
> - ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
> - if (ret)
> - dev_warn(panel->dev, "failed to enter sleep mode: %d\n", ret);
> + /* Attempt to enter sleep mode even if display off failed. */
> + dsi_ctx.accum_err = 0;
> + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
>
> msleep(120);
>
> @@ -258,6 +232,7 @@ static int rm68200_prepare(struct drm_panel *panel)
> {
> struct rm68200 *ctx = panel_to_rm68200(panel);
> struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
> + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
> int ret;
>
> ret = regulator_enable(ctx->supply);
> @@ -273,19 +248,18 @@ static int rm68200_prepare(struct drm_panel *panel)
> msleep(100);
> }
>
> - rm68200_init_sequence(ctx);
> + rm68200_init_sequence(&dsi_ctx);
>
> - ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
> - if (ret)
> - goto assert_reset;
> + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
>
> - msleep(125);
> + mipi_dsi_msleep(&dsi_ctx, 125);
>
> - ret = mipi_dsi_dcs_set_display_on(dsi);
> + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
> + ret = dsi_ctx.accum_err;
> if (ret)
> goto assert_reset;
>
> - msleep(20);
> + mipi_dsi_msleep(&dsi_ctx, 20);
>
> return 0;
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Thanks,
Neil
next prev parent reply other threads:[~2026-11-02 13:02 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-02 4:32 [PATCH v2 0/5] drm/panel: Use mipi_dsi_*_multi() in feiyang and rm68200 Hsieh Hung-En
2026-11-02 4:32 ` [PATCH v2 1/5] drm/panel: feiyang-fy07024di26a30d: Fix prepare error cleanup Hsieh Hung-En
2026-11-02 13:00 ` neil.armstrong
2026-11-02 4:32 ` [PATCH v2 2/5] drm/panel: raydium-rm68200: " Hsieh Hung-En
2026-11-02 13:01 ` neil.armstrong
2026-11-02 4:32 ` [PATCH v2 3/5] drm/panel: feiyang-fy07024di26a30d: Use mipi_dsi_*_multi() functions Hsieh Hung-En
2026-11-02 13:02 ` neil.armstrong
2026-11-02 4:32 ` [PATCH v2 4/5] drm/panel: raydium-rm68200: " Hsieh Hung-En
2026-11-02 13:02 ` neil.armstrong [this message]
2026-11-02 4:32 ` [PATCH v2 5/5] drm/panel: raydium-rm68200: Use lowercase hex literals Hsieh Hung-En
2026-11-02 13:02 ` neil.armstrong
2026-11-02 13:40 ` [PATCH v2 0/5] drm/panel: Use mipi_dsi_*_multi() in feiyang and rm68200 Neil Armstrong
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