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Fri, 01 Aug 2025 01:28:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFXzVMpoNTOUr+QJdVXJ84SNHSBTQYxIJbq36BDLV4wmlovxf8sqtvX2B9vl9qw1lN1AHJg7w== X-Received: by 2002:a17:903:283:b0:231:c3c1:babb with SMTP id d9443c01a7336-24200b0f9f0mr71691545ad.18.1754036887597; Fri, 01 Aug 2025 01:28:07 -0700 (PDT) Received: from [10.218.42.132] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-241e89a3acfsm37009225ad.146.2025.08.01.01.28.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 01 Aug 2025 01:28:07 -0700 (PDT) Message-ID: <7bac637b-9483-4341-91c0-e31d5c2f0ea3@oss.qualcomm.com> Date: Fri, 1 Aug 2025 13:58:00 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/3] opp: Add bw_factor support to adjust bandwidth dynamically To: Viresh Kumar Cc: Viresh Kumar , Nishanth Menon , Stephen Boyd , "Rafael J. Wysocki" , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Conor Dooley , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org References: <20250717-opp_pcie-v1-0-dde6f452571b@oss.qualcomm.com> <0dfe9025-de00-4ec2-b6ca-5ef8d9414301@oss.qualcomm.com> <20250801072845.ppxka4ry4dtn6j3m@vireshk-i7> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <20250801072845.ppxka4ry4dtn6j3m@vireshk-i7> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: hT0bJIwt6H4sybs6qSEl81H78IN2B1O7 X-Authority-Analysis: v=2.4 cv=Wv0rMcfv c=1 sm=1 tr=0 ts=688c7a99 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=9P8yD98ns4tQo_T1VPoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: hT0bJIwt6H4sybs6qSEl81H78IN2B1O7 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODAxMDA2MCBTYWx0ZWRfX4sluENBoTEeQ ky6MjANA2EfSH8YxonKub1P0onbqQmkdFMq73DzBXKErftP3wC10OoUn9zxbAWPU/7P+q16ufif 2+RzWiUTMs1fRCjbeSeqRG1NqCCON9J73TD2tI6mFiO2p7fLEfSWmn/Q8c7sclTNtGVEnhSF5xy Pz6IQj3gdEpUz8OgjKG81IkQApHdCqC7+3QXkJHEVY1QMtuc5u5AJ6bRZ4CJzoXwmtsi/EwrJb8 4EcsyvRF/2GIRCDVsSt8jNwtJxGudqHuiCSKLUzEvsWToDJjMuZIple0QskpYrbspkmKT+AXQE+ pf48j6j8/hLvUCipjw6hS3xkwjXNcphXkwBx0EiguPusoMDzj1mw/ja+jqH+B9Uf4Zvh4TpB8Mc WeoopqJhepHDhT0koBMCj1zXm+1YrjCZEqOt7wTDRWFICWeVdPlGYPcqz5qojV6fV5mKJtsA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-01_02,2025-07-31_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 mlxscore=0 adultscore=0 impostorscore=0 phishscore=0 mlxlogscore=800 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2508010060 On 8/1/2025 12:58 PM, Viresh Kumar wrote: > On 01-08-25, 12:05, Krishna Chaitanya Chundru wrote: >> Can you please review this once. > > Sorry about the delay. > >>> The existing OPP table in the device tree for PCIe is shared across >>> different link configurations such as data rates 8GT/s x2 and 16GT/s x1. >>> These configurations often operate at the same frequency, allowing them >>> to reuse the same OPP entries. However, 8GT/s and 16 GT/s may have >>> different characteristics beyond frequency—such as RPMh votes in QCOM >>> case, which cannot be represented accurately when sharing a single OPP. > > From the looks of it, something like this should also work: > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 54c6d0fdb2af..0a76bc4c4dc9 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -2216,18 +2216,12 @@ opp-2500000 { > opp-peak-kBps = <250000 1>; > }; > > - /* GEN 1 x2 and GEN 2 x1 */ > + /* GEN 2 x1 */ > opp-5000000 { > opp-hz = /bits/ 64 <5000000>; > required-opps = <&rpmhpd_opp_low_svs>; > - opp-peak-kBps = <500000 1>; > - }; > - > - /* GEN 2 x2 */ > - opp-10000000 { > - opp-hz = /bits/ 64 <10000000>; > - required-opps = <&rpmhpd_opp_low_svs>; > - opp-peak-kBps = <1000000 1>; > + opp-peak-kBps-x1 = <500000 1>; > + opp-peak-kBps-x2 = <1000000 1>; > }; > > /* GEN 3 x1 */ > @@ -2237,18 +2231,12 @@ opp-8000000 { > opp-peak-kBps = <984500 1>; > }; > > - /* GEN 3 x2 and GEN 4 x1 */ > + /* GEN 4 x1 */ > opp-16000000 { > opp-hz = /bits/ 64 <16000000>; > required-opps = <&rpmhpd_opp_nom>; > - opp-peak-kBps = <1969000 1>; > - }; > - > - /* GEN 4 x2 */ > - opp-32000000 { > - opp-hz = /bits/ 64 <32000000>; > - required-opps = <&rpmhpd_opp_nom>; > - opp-peak-kBps = <3938000 1>; > + opp-peak-kBps-x1 = <1969000 1>; > + opp-peak-kBps-x2 = <3938000 1>; > }; > }; > > The OPP core supports named properties, which will make this work. Hi Viresh, When ever PCIe link speed/width changes we need to update the OPP votes, If we use named properties approach we might not be able to change it dynamically without removing the OPP table first. For that reason only we haven't used that approach. Correct us if our understanding is wrong. - Krishna Chaitanya. >