From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from ixit.cz (ixit.cz [185.100.197.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D527381B07; Tue, 3 Mar 2026 18:15:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.100.197.86 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772561716; cv=none; b=Iqeqlsv1G0K8cCaxjP+CFx3ZTR7WWyFIODnkfagvRSl43wwjMGJv/xL1hR8Cskr0Vb7l8Fh0h+mXlNQav6RTaAeN71PIFAqo4zps9PYacx9+6pCVaXwZOAkA9paf52jBRP7/LeeTAc8PDrw43TpexIVj2xh1SpUAzR/aggOaV+o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772561716; c=relaxed/simple; bh=4TTpOPJIVrYRzF4VduTyERqWyy/UhdOuRAeGDElHi5c=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=qV77n7jRd+BicBVtemEfjXrXfHcowBNFBRDSCpOTq9I6shEtV666xt1iA45Ls0Ss0O4EpD3Y2selLnt7wBm/Tr/KolcTsrEHqPJY8YP1ApmDsvee0sj+BZmQwgrua+LfP8yGitV6TlY8CZRycJ9wlJ2MoJaAODpJlpnqefok0Z0= ARC-Authentication-Results:i=1; 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bh=zRSFB+Kow30kkyNQlPlB1H4dALbfz4Gh6BYXFVdhCK4=; b=hQAbXY4ZflAn48ecmR/w9PncxD6iQM73aeR+ItGW2FGeaCdaYE3p0zAweg7Qpz7/ytG3yS WkL5bYLQd4aKRxO5UI+yBG5jJ1xjZA46iMZF7naSJAmHQMaogdPEazlyKdh4Mol7P5ZRPs YWNnr4Kka+DrEHXh9zf0Z9TejKx68Gg= Message-ID: <7bccfc13-de1b-4464-b97f-ee9e98a8713a@ixit.cz> Date: Tue, 3 Mar 2026 19:14:59 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/3] arm64: dts: rockchip: Use reference PCIe clock generator for BPI-R2-Pro To: Charalampos Mitrodimas Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Martin Filla , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260303-rk3568-bri-r2-pro-fix-pcie-v2-0-04665e55d5a8@ixit.cz> <20260303-rk3568-bri-r2-pro-fix-pcie-v2-2-04665e55d5a8@ixit.cz> <87fr6gn780.fsf@posteo.net> Content-Language: en-US From: David Heidelberg Autocrypt: addr=david@ixit.cz; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 03/03/2026 18:38, Charalampos Mitrodimas wrote: > David Heidelberg via B4 Relay writes: > >> From: David Heidelberg >> >> Describe properly PCIe clock, which allows us correct the >> toplogy (removing the vcc3v3-{minipcie,ngff} dependency on pi6c as >> supply) and adding the clock dependency in the PCIe nodes. >> >> Suggested-by: Heiko Stuebner >> Tested-by: Martin Filla >> Signed-off-by: David Heidelberg >> --- >> arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 45 +++++++++++++++------- >> 1 file changed, 31 insertions(+), 14 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts >> index d02b82c5f979a..a071cb67579c4 100644 >> --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts >> +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts >> @@ -120,18 +120,13 @@ pcie_refclk_gen: pcie-refclk-gen-clock { >> clock-frequency = <100000000>; >> }; >> >> - vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 { >> - compatible = "regulator-fixed"; >> - regulator-name = "vcc3v3_pcie"; >> - regulator-min-microvolt = <3300000>; >> - regulator-max-microvolt = <3300000>; >> - enable-active-high; >> - gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; >> - startup-delay-us = <200000>; >> - vin-supply = <&vcc5v0_sys>; >> + pcie_refclk: pcie-refclk-clock { >> + compatible = "gpio-gate-clock"; >> + clocks = <&pcie_refclk_gen>; >> + #clock-cells = <0>; >> + enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; >> }; >> >> - /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ >> vcc3v3_minipcie: regulator-vcc3v3-minipcie { >> compatible = "regulator-fixed"; >> regulator-name = "vcc3v3_minipcie"; >> @@ -142,10 +137,9 @@ vcc3v3_minipcie: regulator-vcc3v3-minipcie { >> pinctrl-names = "default"; >> pinctrl-0 = <&minipcie_enable_h>; >> startup-delay-us = <50000>; >> - vin-supply = <&vcc3v3_pi6c_05>; >> + vin-supply = <&vcc3v3_sys>; >> }; >> >> - /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ >> vcc3v3_ngff: regulator-vcc3v3-ngff { >> compatible = "regulator-fixed"; >> regulator-name = "vcc3v3_ngff"; >> @@ -156,7 +150,7 @@ vcc3v3_ngff: regulator-vcc3v3-ngff { >> pinctrl-names = "default"; >> pinctrl-0 = <&ngffpcie_enable_h>; >> startup-delay-us = <50000>; >> - vin-supply = <&vcc3v3_pi6c_05>; >> + vin-supply = <&vcc3v3_sys>; >> }; >> >> vcc5v0_usb: regulator-vcc5v0-usb { >> @@ -586,12 +580,23 @@ rgmii_phy1: ethernet-phy@0 { >> >> &pcie30phy { >> data-lanes = <1 2>; >> - phy-supply = <&vcc3v3_pi6c_05>; >> + >> status = "okay"; >> }; >> >> &pcie3x1 { >> /* M.2 slot */ >> + /* >> + * The board has a gpio-controlled "pcie_refclk" generator, >> + * so add it to the list of clocks. >> + */ >> + clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, >> + <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, >> + <&cru CLK_PCIE30X1_AUX_NDFT>, >> + <&pcie_refclk>; >> + clock-names = "aclk_mst", "aclk_slv", >> + "aclk_dbi", "pclk", "aux", >> + "ref"; > > Hi, > > The DT binding in rockchip-dw-pcie-common.yaml defines clock-names as a > positional array: > > items: > - const: aclk_mst > - const: aclk_slv > - const: aclk_dbi > - const: pclk > - const: aux > - const: pipe <-- position 5 > - const: ref <-- position 6 > > With "ref" at position 5, this would fail dtbs_check because the schema > expects "pipe" there. > > Other boards that include the ref clock (rk3588-rock-5-itx, > rk3588-jaguar) include "pipe" at position 5 and "ref" at position 6. The > rk3568 has CLK_PCIE30X1_PIPE_DFT available in the CRU header. > > Should the pipe clock be included before ref to match the binding > schema? Good catch, I'll put pipe before the ref addition. I'll let my friend test these changes and I'll submit another version incl the pipe. David [...]