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[93.144.65.244]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4601f2dcad5sm58222519f8f.5.2026.06.08.07.41.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jun 2026 07:41:36 -0700 (PDT) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: pierluigi.p@variscite.com, Stefano Radaelli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Subject: [PATCH v5 13/14] arm64: dts: imx8mp-var-som-symphony: add second Ethernet port Date: Mon, 8 Jun 2026 16:41:14 +0200 Message-ID: <7bcfeb748665154245f5dc3294b82ab79d96e4a1.1780929317.git.stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Stefano Radaelli Add support for the second Ethernet interface available on the Symphony carrier board. Enable the FEC controller, add the MaxLinear MXL86110 Gigabit Ethernet PHY on the MDIO bus, describe its reset and power configuration, and add the required RGMII pinctrl settings. Signed-off-by: Stefano Radaelli --- v4->v5: - Remove regulator-always-on and duplicated vddio node v3->v4: - Fixed eth regulator v2->v3: - Add FEC controller and MaxLinear MXL86110 PHY support .../dts/freescale/imx8mp-var-som-symphony.dts | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 93dee9ec0b9b..e928a3d44b1d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -66,6 +66,16 @@ pcie0_refclk: pcie0-refclk { clock-frequency = <100000000>; }; + reg_fec_phy: regulator-fec-phy { + compatible = "regulator-fixed"; + regulator-name = "fec-phy"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <20000>; + gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -106,6 +116,33 @@ &ecspi2 { status = "okay"; }; +&eqos { + mdio { + ethphy1: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + vddio-supply = <®_phy_vddio>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + phy-supply = <®_fec_phy>; + status = "okay"; +}; + &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; @@ -363,6 +400,23 @@ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x12 >; }; + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x00 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x00 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x00 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x00 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x00 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x00 + >; + }; + pinctrl_flexcan2: flexcan2grp { fsl,pins = < MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154 -- 2.47.3