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[78.210.255.2]) by smtp.googlemail.com with ESMTPSA id w16sm11901697wrp.1.2019.02.13.00.48.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 Feb 2019 00:48:26 -0800 (PST) Subject: Re: [v4 PATCH 6/8] clocksource/drivers/riscv: Add required checks during clock source init To: Atish Patra , linux-riscv@lists.infradead.org Cc: Alan Kao , Albert Ou , Andreas Schwab , Anup Patel , Dmitriy Cherkasov , Jason Cooper , Johan Hovold , linux-kernel@vger.kernel.org, Marc Zyngier , Palmer Dabbelt , Paul Walmsley , Rob Herring , Thomas Gleixner References: <1549969812-22502-1-git-send-email-atish.patra@wdc.com> <1549969812-22502-7-git-send-email-atish.patra@wdc.com> From: Daniel Lezcano Message-ID: <7bd250fb-c896-64e1-d73b-6f3dd284e2d6@linaro.org> Date: Wed, 13 Feb 2019 09:48:24 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <1549969812-22502-7-git-send-email-atish.patra@wdc.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/02/2019 12:10, Atish Patra wrote: > Currently, clocksource registration happens for an invalid cpu for > non-smp kernels. This lead to kernel panic as cpu hotplug registration > will fail for those cpus. Moreover, riscv_hartid_to_cpuid can return > errors now. > > Do not proceed if hartid or cpuid is invalid. Take this opprtunity to > print appropriate error strings for different failure cases. > > Signed-off-by: Atish Patra Do you want me to take it through my tree ? > --- > drivers/clocksource/timer-riscv.c | 23 ++++++++++++++++++++--- > 1 file changed, 20 insertions(+), 3 deletions(-) > > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c > index 43189220..e8163693 100644 > --- a/drivers/clocksource/timer-riscv.c > +++ b/drivers/clocksource/timer-riscv.c > @@ -95,13 +95,30 @@ static int __init riscv_timer_init_dt(struct device_node *n) > struct clocksource *cs; > > hartid = riscv_of_processor_hartid(n); > + if (hartid < 0) { > + pr_warn("Not valid hartid for node [%pOF] error = [%d]\n", > + n, hartid); > + return hartid; > + } > + > cpuid = riscv_hartid_to_cpuid(hartid); > + if (cpuid < 0) { > + pr_warn("Invalid cpuid for hartid [%d]\n", hartid); > + return cpuid; > + } > > if (cpuid != smp_processor_id()) > return 0; > > + pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n", > + __func__, cpuid, hartid); > cs = per_cpu_ptr(&riscv_clocksource, cpuid); > - clocksource_register_hz(cs, riscv_timebase); > + error = clocksource_register_hz(cs, riscv_timebase); > + if (error) { > + pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", > + error, cpuid); > + return error; > + } > > sched_clock_register(riscv_sched_clock, > BITS_PER_LONG, riscv_timebase); > @@ -110,8 +127,8 @@ static int __init riscv_timer_init_dt(struct device_node *n) > "clockevents/riscv/timer:starting", > riscv_timer_starting_cpu, riscv_timer_dying_cpu); > if (error) > - pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", > - error, cpuid); > + pr_err("cpu hp setup state failed for RISCV timer [%d]\n", > + error); > return error; > } > > -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog