From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 516DB2ECEBF; Thu, 21 Aug 2025 08:52:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755766368; cv=none; b=svDv/fbRZo3VZhZYWNcIMJZU2lr898oii5u3wVDPYjhWmrTJsIVD6UtlukTsWOPsTZgx19CP9PvjbAL2LFrqK0p7KyFee1+z/qG/Wkopri9TpKFipfEBmaeK9RKgG2uXim+S97pl7+4swV7o+OvQRSHmF5xvv9v1nh2mFrFZBFg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755766368; c=relaxed/simple; bh=C2dlNnaM7u0qj7k51quVsQ//aocjvVqHYJx7fh3mPJo=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=bfPzoxzKay03Ifj6dro7ru4qtj4O585o3ksLmqNShW20EPGk8z0t7vbTo3J7JbxiGhkULouoe+Sx5pqpabkfYpvUSnXAomx14/QpC7//UlG8j64P9jztoq+oEvHqxC3cEFVPY/vr6gcxJLgV23VCh3wOzEQcFsldf1jTe4ChdqE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=u6/Fb0yb; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="u6/Fb0yb" Received: from [192.168.88.20] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id D3A04C78; Thu, 21 Aug 2025 10:51:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1755766303; bh=C2dlNnaM7u0qj7k51quVsQ//aocjvVqHYJx7fh3mPJo=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=u6/Fb0yb36ohZvE0nOc6wbVrQqeEvju5gYPLx5Pm3Lt3BQVxj8UAevRJeINKkII4J jCTPGKhv3ksUPsyLardwccR7ZUGheew8S7/fpGigQxq+Vq3JmhU8W97+/lVY+KrPYR hIer/A+U+tvqTVzXMJH7QOnH2VnL2Q3GWyjqEvTk= Message-ID: <7bffc8e2-ccdd-4a92-bbc6-95c7c99d7e4a@ideasonboard.com> Date: Thu, 21 Aug 2025 11:52:38 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 5/6] drm: renesas: rz-du: mipi_dsi: Add support for LPCLK clock handling To: Prabhakar Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Fabrizio Castro , Tommaso Merciai , Lad Prabhakar , Geert Uytterhoeven , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Biju Das , Magnus Damm References: <20250728201435.3505594-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20250728201435.3505594-6-prabhakar.mahadev-lad.rj@bp.renesas.com> Content-Language: en-US From: Tomi Valkeinen In-Reply-To: <20250728201435.3505594-6-prabhakar.mahadev-lad.rj@bp.renesas.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi, On 28/07/2025 23:14, Prabhakar wrote: > From: Lad Prabhakar > > Add LPCLK clock support in the RZ/G2L MIPI DSI driver via the optional > clock API. This clock is required by some SoCs like RZ/V2H(P) for proper > DPHY configuration, whereas it is absent on others like RZ/G2L. In the DT binding lpclk is present for all SoCs. Is that an error in the binding, then? And if I read the binding correctly, it's mandatory for all SoCs, so why is it optional in the driver? Tomi > Introduce a new `lpclk` field in the `rzg2l_mipi_dsi` structure and > conditionally acquire the "lpclk" clock using `devm_clk_get_optional()` > during probe. This allows LPCLK-aware SoCs to pass the clock via device > tree without impacting existing platforms. > > Co-developed-by: Fabrizio Castro > Signed-off-by: Fabrizio Castro > Signed-off-by: Lad Prabhakar > Reviewed-by: Biju Das > --- > v6->v7: > - New patch > Note, this patch was previously part of series [0]. > [0] https://lore.kernel.org/all/20250609225630.502888-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ > --- > drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > index f87337c3cbb5..893a90c7a886 100644 > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > @@ -68,6 +68,7 @@ struct rzg2l_mipi_dsi { > struct drm_bridge *next_bridge; > > struct clk *vclk; > + struct clk *lpclk; > > enum mipi_dsi_pixel_format format; > unsigned int num_data_lanes; > @@ -979,6 +980,10 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) > if (IS_ERR(dsi->vclk)) > return PTR_ERR(dsi->vclk); > > + dsi->lpclk = devm_clk_get_optional(dsi->dev, "lpclk"); > + if (IS_ERR(dsi->lpclk)) > + return PTR_ERR(dsi->lpclk); > + > dsi->rstc = devm_reset_control_get_optional_exclusive(dsi->dev, "rst"); > if (IS_ERR(dsi->rstc)) > return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc),