From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC27DC433EF for ; Tue, 21 Jun 2022 03:12:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344993AbiFUDMF (ORCPT ); Mon, 20 Jun 2022 23:12:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344989AbiFUDL7 (ORCPT ); Mon, 20 Jun 2022 23:11:59 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 070511FA4B; Mon, 20 Jun 2022 20:11:57 -0700 (PDT) X-UUID: f42fc7d779dd466d86a6b54c2315ef00-20220621 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:05b7a6f9-0bf1-4f2f-b9bb-873c83cb3b13,OB:0,LO B:10,IP:0,URL:0,TC:0,Content:2,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,AC TION:release,TS:47 X-CID-INFO: VERSION:1.1.6,REQID:05b7a6f9-0bf1-4f2f-b9bb-873c83cb3b13,OB:0,LOB: 10,IP:0,URL:0,TC:0,Content:2,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:47 X-CID-META: VersionHash:b14ad71,CLOUDID:06db0fea-f7af-4e69-92ee-0fd74a0c286c,C OID:03753ab33708,Recheck:0,SF:28|17|19|48,TC:nil,Content:4,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: f42fc7d779dd466d86a6b54c2315ef00-20220621 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1915420034; Tue, 21 Jun 2022 11:11:55 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 21 Jun 2022 11:11:55 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 21 Jun 2022 11:11:55 +0800 Message-ID: <7bffe5226a80474f150ef67e36d2b75ea8e8a9d8.camel@mediatek.com> Subject: Re: [PATCH v12 11/14] drm/mediatek: dpi: Add tvd_clk enable/disable flow From: Rex-BC Chen To: CK Hu , , , , , , , CC: , , , , , , , , , , Date: Tue, 21 Jun 2022 11:11:55 +0800 In-Reply-To: <218de671054a2c02d47a0bb4a31a0b07d24d7eee.camel@mediatek.com> References: <20220620121028.29234-1-rex-bc.chen@mediatek.com> <20220620121028.29234-12-rex-bc.chen@mediatek.com> <218de671054a2c02d47a0bb4a31a0b07d24d7eee.camel@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2022-06-21 at 10:55 +0800, CK Hu wrote: > Hi, Bo-Chen: > > On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote: > > We should enable/disable tvd_clk when power_on/power_off, so add > > this > > patch to do this. > > Without this patch, what would happen? > It seems this patch is redundant for these SoCs: > > static const struct of_device_id mtk_dpi_of_ids[] = { > { .compatible = "mediatek,mt2701-dpi", > .data = &mt2701_conf, > }, > { .compatible = "mediatek,mt8173-dpi", > .data = &mt8173_conf, > }, > { .compatible = "mediatek,mt8183-dpi", > .data = &mt8183_conf, > }, > { .compatible = "mediatek,mt8192-dpi", > .data = &mt8192_conf, > }, > { }, > }; > > Regards, > CK > Hello CK, IMO, this is a bug fix patch. From the usage of clock, if we want to use it, we should enable it . Therefore, I think we should add this and I will add a fix tag for this patch. BRs, Bo-Chen > > > > > Signed-off-by: Bo-Chen Chen > > --- > > drivers/gpu/drm/mediatek/mtk_dpi.c | 11 ++++++++++- > > 1 file changed, 10 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c > > b/drivers/gpu/drm/mediatek/mtk_dpi.c > > index 2717b1741b7a..f83ecb154457 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > > @@ -455,6 +455,7 @@ static void mtk_dpi_power_off(struct mtk_dpi > > *dpi) > > mtk_dpi_disable(dpi); > > clk_disable_unprepare(dpi->pixel_clk); > > clk_disable_unprepare(dpi->engine_clk); > > + clk_disable_unprepare(dpi->tvd_clk); > > } > > > > static int mtk_dpi_power_on(struct mtk_dpi *dpi) > > @@ -464,10 +465,16 @@ static int mtk_dpi_power_on(struct mtk_dpi > > *dpi) > > if (++dpi->refcount != 1) > > return 0; > > > > + ret = clk_prepare_enable(dpi->tvd_clk); > > + if (ret) { > > + dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", > > ret); > > + goto err_refcount; > > + } > > + > > ret = clk_prepare_enable(dpi->engine_clk); > > if (ret) { > > dev_err(dpi->dev, "Failed to enable engine clock: > > %d\n", ret); > > - goto err_refcount; > > + goto err_engine; > > } > > > > ret = clk_prepare_enable(dpi->pixel_clk); > > @@ -484,6 +491,8 @@ static int mtk_dpi_power_on(struct mtk_dpi > > *dpi) > > > > err_pixel: > > clk_disable_unprepare(dpi->engine_clk); > > +err_engine: > > + clk_disable_unprepare(dpi->tvd_clk); > > err_refcount: > > dpi->refcount--; > > return ret; > >