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Wed, 29 Oct 2025 03:26:31 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: AMptcG-LwCSF Date: Wed, 29 Oct 2025 08:26:11 +0100 From: "Arnd Bergmann" To: "Ryan Chen" , "Andrew Lunn" Cc: BMC-SW , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Joel Stanley" , "Andrew Jeffery" , "Jeremy Kerr" , "Lee Jones" , "Catalin Marinas" , "Will Deacon" , "Bjorn Andersson" , "Geert Uytterhoeven" , "Nishanth Menon" , =?UTF-8?Q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , "Taniya Das" , "Lad, Prabhakar" , "Kuninori Morimoto" , "Eric Biggers" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-aspeed@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" Message-Id: <7c0c966b-c45f-47ad-9243-b945036a9bd2@app.fastmail.com> In-Reply-To: References: <20251022070543.1169173-1-ryan_chen@aspeedtech.com> <20251022070543.1169173-5-ryan_chen@aspeedtech.com> <6a97fbb4-19c2-4ffa-9c73-26aea02c27e4@app.fastmail.com> <71df9bdf-53b2-45e2-a9e3-5b00a556f957@lunn.ch> <01573262-69a8-44cf-ae02-2e9842c59dde@lunn.ch> Subject: Re: [PATCH v6 4/6] arm64: dts: aspeed: Add initial AST2700 SoC device tree Content-Type: text/plain Content-Transfer-Encoding: 7bit On Wed, Oct 29, 2025, at 03:31, Ryan Chen wrote: >> Subject: Re: [PATCH v6 4/6] arm64: dts: aspeed: Add initial AST2700 SoC device >> tree >> >> On Mon, Oct 27, 2025 at 02:42:01AM +0000, Ryan Chen wrote: >> > > Subject: Re: [PATCH v6 4/6] arm64: dts: aspeed: Add initial AST2700 >> > > SoC device tree >> > > >> > > > SoC0, referred to as the CPU die, contains a dual-core Cortex-A35 >> > > > cluster and two Cortex-M4 cores, along with its own clock/reset >> > > > domains and high-speed peripheral set. >> > > >> > > > SoC1, referred to as the I/O die, contains the Boot MCU and its >> > > > own clock/reset domains and low-speed peripheral set, and is >> > > > responsible for system boot and control functions. >> > > >> > > So is the same .dtsi file shared by both systems? >> > >> > This .dtsi represents the Cortex-A35 view only and is not shared with >> > the Cortex-M4 or the Boot MCU side, since they are separate 32-bit and >> > 64-bit systems running independent firmware. >> >> DT describes the hardware. The .dtsi file could be shared, you just need >> different status = <>; lines in the dtb blob. > > Could you please share an example of a .dtsi that is shared between > different CPU architectures? I can think of three that are shared between arm and riscv, with both able to boot Linux using a variation of the same device tree, with the .dtsi file being included from the respective other side: arch/riscv/boot/dts/renesas/r9a07g043f.dtsi arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi arch/arm64/boot/dts/sophgo/sg2000.dtsi All of these however use the same basic physical address layout as seen from the two CPUs, with only the set of on-chip devices being slightly different, such as using the native irqchip instance per CPU. > In the AST2700 design, even though we have both Cortex-A35 (64-bit) > and Cortex-M4 (32-bit) cores, each runs in a distinct address space > and sees a different memory map. This is similar to the Cortex-M4 on i.MX7D. This is supported by the Linux code, but I don't see the corresponding dts file for it now, it may have never been merged. If you want to share the devicetree source files but have different physical addresses, you'll need to set up 'ranges' properties in the top-level .dtsi files that map the child buses into the CPU space as needed. arch/arm64/boot/dts/apple/t6002.dtsi has a rather sophisticated way of doing this where &die0 and &die1 set up the ranges for including the same child die multiple times at different addresses. You should be able to use similar method but make it a lot simpler for your case. Arnd