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Fri, 24 Oct 2025 07:23:10 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF4MPeSwFhzPTKvaKRf1XESN9sP6R6a1VjFKBw7Sdaagyby5CvwLmehW1f6noOGu/6x8AKqOA== X-Received: by 2002:a17:902:f64a:b0:294:7048:643 with SMTP id d9443c01a7336-29470480f8fmr67499295ad.15.1761315790217; Fri, 24 Oct 2025 07:23:10 -0700 (PDT) Received: from [10.204.104.20] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-33e1ed68869sm5129253a91.0.2025.10.24.07.23.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Oct 2025 07:23:09 -0700 (PDT) Message-ID: <7c563e83-031c-445c-bcfa-c04f4729622d@oss.qualcomm.com> Date: Fri, 24 Oct 2025 19:53:03 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/6] drm/msm/a6xx: Add support for Adreno 612 To: rob.clark@oss.qualcomm.com, Konrad Dybcio Cc: Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jie Zhang References: <20251017-qcs615-spin-2-v1-0-0baa44f80905@oss.qualcomm.com> <20251017-qcs615-spin-2-v1-1-0baa44f80905@oss.qualcomm.com> <44ff81bf-8970-475c-a4f5-c03220bc8c3f@oss.qualcomm.com> <97aeb6a1-fda2-440f-b14b-2f3dbc2d7e8e@oss.qualcomm.com> <5e64c246-a424-42c9-b102-e1a2af579936@oss.qualcomm.com> Content-Language: en-US From: Akhil P Oommen In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDIxMDE5MCBTYWx0ZWRfX35YioKJ7oVmv Sy8CtqPVhm4ogf/Z9x46lQY/1w8vrTa8JLOIS75rSpu/h0y3HlWOrKNGLDR6DUUzV+2blHXIgx5 SwjF0Pw8H4vbtySRTWuaNTyTW0Wi0utipC9HLWwdFI++HpzJc2vfRBDmObmZlBkDEey3lud34n2 OaxqUncJSNEE0DNrMv+N33rzaTJDHzYatrR+sPn0e2VIdQfqDRUAZBlPrQh5jQjvmC/5mnLeMjJ ITLhisnmmumeWt7r2SVXJhnijkmP5YUtLmqYXYbnIGC1x8iKXD7wilGbx3x1AR0LskpqppILbR0 /Rg4+mC+puuv7/Je0PGLa4DJ0abLMqMBlcW8GVo+oWqL+mRBsovJ7X0/GpCr/kMOtHkLwIBqXOt 1M6PXTGFKjX5RH29Bn3O00om/zykkA== X-Authority-Analysis: v=2.4 cv=FbM6BZ+6 c=1 sm=1 tr=0 ts=68fb8bcf cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=Kgau_Mukr_2Uqyo6pRUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: Wfh4m7N1KS5W2T-PfGfhRfI3BhZeZeOZ X-Proofpoint-ORIG-GUID: Wfh4m7N1KS5W2T-PfGfhRfI3BhZeZeOZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-24_02,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 spamscore=0 impostorscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510210190 On 10/24/2025 6:46 PM, Rob Clark wrote: > On Fri, Oct 24, 2025 at 12:55 AM Konrad Dybcio > wrote: >> >> On 10/24/25 12:57 AM, Akhil P Oommen wrote: >>> On 10/22/2025 8:43 PM, Konrad Dybcio wrote: >>>> On 10/17/25 7:08 PM, Akhil P Oommen wrote: >>>>> From: Jie Zhang >>>>> >>>>> Add support for Adreno 612 GPU found in SM6150/QCS615 chipsets. >>>>> A612 falls under ADRENO_6XX_GEN1 family and is a cut down version >>>>> of A615 GPU. >>>>> >>>>> A612 has a new IP called Reduced Graphics Management Unit or RGMU >>>>> which is a small state machine which helps to toggle GX GDSC >>>>> (connected to CX rail) to implement IFPC feature. It doesn't support >>>>> any other features of a full fledged GMU like clock control, resource >>>>> voting to rpmh etc. So we need linux clock driver support like other >>>>> gmu-wrapper implementations to control gpu core clock and gpu GX gdsc. >>>>> This patch skips RGMU core initialization and act more like a >>>>> gmu-wrapper case. >>>>> >>>>> Co-developed-by: Akhil P Oommen >>>>> Signed-off-by: Jie Zhang >>>>> Signed-off-by: Akhil P Oommen >>>>> --- >>>> >>>> [...] >>>> >>>>> @@ -350,12 +350,18 @@ static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = { >>>>> /* Trigger a OOB (out of band) request to the GMU */ >>>>> int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) >>>>> { >>>>> + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); >>>>> + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; >>>>> int ret; >>>>> u32 val; >>>>> int request, ack; >>>>> >>>>> WARN_ON_ONCE(!mutex_is_locked(&gmu->lock)); >>>>> >>>>> + /* Skip OOB calls since RGMU is not enabled */ >>>> >>>> "RGMU doesn't handle OOB calls" >>> >>> Technically RGMU can handle OOB calls. But we are not initializing rgmu. >> >> Oh, I glossed over that.. >> >> IIRC the reason we delayed 612 support in the past was to make sure >> that the RGMU FW is consumed, so that runtime requirements don't >> suddenly change one day. >> >> If you have no interest/way in getting it wholly supported right now, >> can you at least make sure that the driver requests the firmware and >> exits if it's absent? > > adreno_load_gpu() calls adreno_load_fw() first thing, and will bail if > gmu fw is missing. (zap fw is a bit more awkward since that could > come from dt or device table.) Correct. And RGMU firmware is available in linux-firmware repo. -Akhil. > > BR, > -R