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X-CSE-ConnectionGUID: OFEzObQZS+Gl/ZRjtFHQEg== X-CSE-MsgGUID: AkquYbtOQbWpf8MU0rbNMQ== X-IronPort-AV: E=McAfee;i="6700,10204,11333"; a="61451874" X-IronPort-AV: E=Sophos;i="6.13,252,1732608000"; d="scan'208";a="61451874" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2025 11:12:52 -0800 X-CSE-ConnectionGUID: zxXLNLOvQP+skVgiWe8S3g== X-CSE-MsgGUID: M9OVu734TNeiEA/md8FO/w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="147115919" Received: from sj-2308-osc3.sj.altera.com ([10.244.138.69]) by orviesa001.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2025 11:12:50 -0800 Date: Sat, 1 Feb 2025 11:12:51 -0800 (PST) From: matthew.gerlach@linux.intel.com To: Krzysztof Kozlowski cc: lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, joyce.ooi@intel.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, matthew.gerlach@altera.com, peter.colberg@altera.com Subject: Re: [PATCH v5 3/5] arm64: dts: agilex: add dtsi for PCIe Root Port In-Reply-To: <40a3dced-defe-412d-b5b2-efcc9619d172@kernel.org> Message-ID: <7c802294-97f6-3e9-4028-686484a525c5@linux.intel.com> References: <20250127173550.1222427-1-matthew.gerlach@linux.intel.com> <20250127173550.1222427-4-matthew.gerlach@linux.intel.com> <22cb714e-db76-b07-8572-2f70f6848369@linux.intel.com> <40a3dced-defe-412d-b5b2-efcc9619d172@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed On Thu, 30 Jan 2025, Krzysztof Kozlowski wrote: > On 29/01/2025 20:42, matthew.gerlach@linux.intel.com wrote: >> >> >> On Wed, 29 Jan 2025, Krzysztof Kozlowski wrote: >> >>> On 27/01/2025 18:35, Matthew Gerlach wrote: >>>> Add the base device tree for support of the PCIe Root Port >>>> for the Agilex family of chips. >>>> >>>> Signed-off-by: Matthew Gerlach >>>> --- >>>> v3: >>>> - Remove accepted patches from patch set. >>>> >>>> v2: >>>> - Rename node to fix schema check error. >>>> --- >>>> .../intel/socfpga_agilex_pcie_root_port.dtsi | 55 +++++++++++++++++++ >>>> 1 file changed, 55 insertions(+) >>>> create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi >>>> >>>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi >>>> new file mode 100644 >>>> index 000000000000..50f131f5791b >>>> --- /dev/null >>>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi >>>> @@ -0,0 +1,55 @@ >>>> +// SPDX-License-Identifier: GPL-2.0 >>> >>> Odd spaces in SPDX tag. >> >> Yes, there should only be one space. >> >>> >>>> +/* >>>> + * Copyright (C) 2024, Intel Corporation >>>> + */ >>>> +&soc0 { >>>> + aglx_hps_bridges: fpga-bus@80000000 { >>>> + compatible = "simple-bus"; >>>> + reg = <0x80000000 0x20200000>, >>>> + <0xf9000000 0x00100000>; >>>> + reg-names = "axi_h2f", "axi_h2f_lw"; >>> >>> Where is this binding defined? >> >> The bindings for these reg-names are not currently defined anywhere, but > > Then you cannot use them. > >> they are also referenced in the following: >> Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml >> arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts >> I am not exactly sure where the right place is to define them, maybe >> Documentation/devicetree/bindings/arm/intel,socfpga.yaml. On the other >> hand, no code references these names; so it might make sense to just >> remove them. > > In general: nowhere, because simple bus does not have such properties. > It's not about reg-names only - you cannot have reg. You just did not > define here simple-bus. I understand. I will remove reg and reg-names. > > Best regards, > Krzysztof > Thanks for the review, Matthew Gerlach