From: stephane eranian <eranian@googlemail.com>
To: Paul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <peterz@infradead.org>,
linux-kernel@vger.kernel.org, mingo@elte.hu,
perfmon2-devel@lists.sf.net, eranian@google.com
Subject: Re: [PATCH] perf_events: fix validate_event bug
Date: Wed, 25 Nov 2009 06:47:54 +0100 [thread overview]
Message-ID: <7c86c4470911242147u160008d4y50385cb348615df8@mail.gmail.com> (raw)
In-Reply-To: <19212.22371.633313.129961@cargo.ozlabs.ibm.com>
On Tue, Nov 24, 2009 at 11:00 PM, Paul Mackerras <paulus@samba.org> wrote:
> stephane eranian writes:
>
>> That means we can drop is_software_event() in this code and instead
>> define locally
>> in x86 a is_hw_pmu_event() function as event->pmu == &pmu.
>
> I'd have to see the patch, but that doesn't feel entirely right,
> because there is a unique characteristic of software events, compared
> to hardware or breakpoint events: they are never capacity
> constrained. In the past, only hardware events were capacity
> constrained, which meant that all the decisions about whether a group
> could go on could be done in the hardware PMU backend. Now we have
> two sources of capacity constraints, so it may be that a group can't
> go on even if the hardware PMU has capacity. That's going to be
> somewhat interesting to get completely right, I think.
>
I was talking of is_software_event() in the context of the hardware PMU
code. The reason you were using this function is simply to skip
SW events because, as you said, they are never constrained
and also because they are not related to HW PMU.
You are right about HW breakpoints, because now you have a new source of
constraints. Only the breakpoint code knows about those constraints.
It seems to me you have two ways of solving this:
1- push the algorithm to assign events to counters up in the generic code
2- have the generic code invoke all possible constraint sources on each group
I have already said that I would not recommend initially going with 1- because
constraints are very diverse in their nature. It is not as simple as 1 event = 1
bitmask of valid counters. Things can be more dynamic than that, e.g., on AMD64,
whereby for certain events the bitmask depends on what is going on in the other
cores on the socket. There are also similar constraints on advanced
Intel features.
So unlike what I heard early on, constraints are not going away,
instead they are
changing in nature and to something much more complex to deal with.
I believe that until all PMU event assignment logic is implemented in the PMU
specific code, it would be very presumptuous to try and design that
generic algorithm.
So I would go with 2, at least initially.
next prev parent reply other threads:[~2009-11-25 5:47 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-10-22 14:51 Stephane Eranian
2009-11-18 16:46 ` Peter Zijlstra
2009-11-23 13:34 ` stephane eranian
2009-11-23 13:45 ` Peter Zijlstra
2009-11-24 13:18 ` stephane eranian
2009-11-24 22:00 ` Paul Mackerras
2009-11-25 5:47 ` stephane eranian [this message]
2009-11-25 7:55 ` Peter Zijlstra
2009-11-24 13:27 ` Stephane Eranian
2009-11-24 19:03 ` [tip:perf/core] perf_events, x86: Fix " tip-bot for Stephane Eranian
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