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Thu, 11 Jun 2026 05:20:20 -0700 (PDT) X-Received: by 2002:a05:6a20:7fa1:b0:3b3:fce3:a7f8 with SMTP id adf61e73a8af0-3b5e31f33efmr3104280637.15.1781180420116; Thu, 11 Jun 2026 05:20:20 -0700 (PDT) Received: from [10.92.167.195] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c865880cc87sm1827061a12.23.2026.06.11.05.20.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 Jun 2026 05:20:19 -0700 (PDT) Message-ID: <7c94758c-1100-43d9-a0a4-2cb7df947cc9@oss.qualcomm.com> Date: Thu, 11 Jun 2026 17:50:12 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v11 5/6] arm64: dts: qcom: monaco: Add OPP-table for ICE UFS and ICE eMMC nodes To: Abhinaba Rakshit , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Adrian Hunter , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neeraj Soni , Harshal Dev Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org References: <20260609-enable-ice-clock-scaling-v11-0-1cebc8b3275b@oss.qualcomm.com> <20260609-enable-ice-clock-scaling-v11-5-1cebc8b3275b@oss.qualcomm.com> Content-Language: en-US From: Kuldeep Singh In-Reply-To: <20260609-enable-ice-clock-scaling-v11-5-1cebc8b3275b@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: yquAMDw6Sj_acLGFAr8TTy1DcOxx1JZF X-Proofpoint-Spam-Info: AW1haW4tMjYwNjExMDEyNCBTYWx0ZWRfX5oWvfZKgyNGZ lX9f85+lRyTAGvBamzR1WD5S2vVWrOPO1bvQRamC1syhVxgtqZFpvanBYvG+8BPLhy//iQzT4Rh DdAUgI/FkpvLuCmdFkM9nl6PkmlRBUU= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjExMDEyNCBTYWx0ZWRfX2A+8ttSRV5My 14Ctkv1Ky46i5cMJxxdbrbVmN0sMvwyIyocaM2n79ocJsZUpFUYbVsD+J8uzw+89/30+/8E5rQS KR4Ts7CpOuwrUriF/hCIqB0otjXO+0usUdxGYuNbhuWgRhyeY9tNNZkORoHWsWv1tQkoYCq4hTl w4vrnkJ1cbdkNeP81w0xUtxZtzS+peUWGctXYlkvsDyI/3rLJxB6+FWXSds21wm11i/x4In5VvY e3w3Pj98khbW1tJN3C5NYF7tnuHEQUcSVas0pjqVMERtJEqNNURV2Nbfj3cU/Y8IOL0KiPz9BoN dsW7SktThdwpGAFsgndxBJh+quh1ABHfCxKyv29KztVibwaE6htelmgFTC2WMUk6PQ5DqNNM43l FZDWCz4JJ8StjBn7znJvnxUhjzg435KXunpWHItVI2oDL032ZARqo+QxmF36i1xm3h+Z4pDY8pc QWO6hX5HC0t/X7hMeLQ== X-Authority-Analysis: v=2.4 cv=F5lnsKhN c=1 sm=1 tr=0 ts=6a2aa805 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=QRdWpJMrku1fmPn5X40A:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-ORIG-GUID: yquAMDw6Sj_acLGFAr8TTy1DcOxx1JZF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-11_02,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 adultscore=0 bulkscore=0 suspectscore=0 impostorscore=0 priorityscore=1501 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606110124 On 09-06-2026 03:17, Abhinaba Rakshit wrote: > Qualcomm Inline Crypto Engine (ICE) platform driver now, supports > an optional OPP-table. > > Add OPP-table for ICE UFS and ICE eMMC device nodes for Monaco > platform. > > Signed-off-by: Abhinaba Rakshit > --- > arch/arm64/boot/dts/qcom/monaco.dtsi | 37 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi > index a1b6e6211b84d0d5008231c55613a0ccd61b9450..d9298d8b7874b8669b2cded2a28a99dce6eadbda 100644 > --- a/arch/arm64/boot/dts/qcom/monaco.dtsi > +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi > @@ -2742,6 +2742,27 @@ ice: crypto@1d88000 { > clock-names = "core", > "iface"; > power-domains = <&gcc GCC_UFS_PHY_GDSC>; > + > + operating-points-v2 = <&ice_opp_table>; > + > + ice_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-75000000 { > + opp-hz = /bits/ 64 <75000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-201600000 { > + opp-hz = /bits/ 64 <201600000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-403200000 { > + opp-hz = /bits/ 64 <403200000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > }; > > crypto: crypto@1dfa000 { > @@ -4878,6 +4899,22 @@ sdhc_ice: crypto@87c8000 { > clock-names = "core", > "iface"; > power-domains = <&rpmhpd RPMHPD_CX>; > + > + operating-points-v2 = <&ice_mmc_opp_table>; s/ice_mmc_opp_table/sdhc_ice_opp_table? -- Regards Kuldeep