From: Vladimir Kondratiev <Vladimir.Kondratiev@mobileye.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>, Gary Guo <gary@garyguo.net>,
Yury Norov <yury.norov@gmail.com>,
Rasmus Villemoes <linux@rasmusvillemoes.dk>,
cfu@wavecomp.com, torvalds@linux-foundation.org, olof@lixom.net,
aleksa.paunovic@htecgroup.com, arikalo@gmail.com,
Boqun Feng <boqun@kernel.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 0/2] riscv: support CPUs with Zalrsc but not Zaamo
Date: Mon, 26 Oct 2026 13:06:02 +0200 [thread overview]
Message-ID: <7cd3e85b-9602-460c-ae90-f0817a6c0c45@mobileye.com> (raw)
In-Reply-To: <20261026103014.GC2668200@noisy.programming.kicks-ass.net>
On 10/26/26 12:30, Peter Zijlstra wrote:
> The comment with RISCV_QUEUED_SPINLOCKS state that Zalrsc requires that
> cmpxchg() loops have forward progress; which is much stronger than the
> typical LL/SC implementation.
>
> Does this MIPS thing indeed provide this?
You mean Ziccrse extension? Yes, p8700 does provide it. I explicitly
confirmed it with hardware designers.
In fact, I use RISCV_QUEUED_SPINLOCKS on this platform
Thanks, Vladimir
prev parent reply other threads:[~2026-10-26 11:06 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-26 9:20 Vladimir Kondratiev
2026-10-26 9:20 ` [PATCH v3 1/2] riscv: build kernel atomics from LR/SC when Zaamo is disabled Vladimir Kondratiev
2026-10-26 9:20 ` [PATCH v3 2/2] riscv: accept the atomic extensions this kernel was built with Vladimir Kondratiev
2026-10-26 10:30 ` [PATCH v3 0/2] riscv: support CPUs with Zalrsc but not Zaamo Peter Zijlstra
2026-10-26 11:06 ` Vladimir Kondratiev [this message]
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