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Tue, 11 Nov 2025 10:08:58 -0800 (PST) Received: from [192.168.10.81] ([176.206.111.214]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4775cd45466sm379917565e9.0.2025.11.11.10.08.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Nov 2025 10:08:58 -0800 (PST) Message-ID: <7cff2a78-94f3-4746-9833-c2a1bf51eed6@redhat.com> Date: Tue, 11 Nov 2025 19:08:56 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v1 02/20] KVM: x86: Refactor GPR accessors to differentiate register access types To: "Chang S. Bae" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: seanjc@google.com, chao.gao@intel.com, zhao1.liu@intel.com References: <20251110180131.28264-1-chang.seok.bae@intel.com> <20251110180131.28264-3-chang.seok.bae@intel.com> From: Paolo Bonzini Content-Language: en-US Autocrypt: addr=pbonzini@redhat.com; keydata= xsEhBFRCcBIBDqDGsz4K0zZun3jh+U6Z9wNGLKQ0kSFyjN38gMqU1SfP+TUNQepFHb/Gc0E2 CxXPkIBTvYY+ZPkoTh5xF9oS1jqI8iRLzouzF8yXs3QjQIZ2SfuCxSVwlV65jotcjD2FTN04 hVopm9llFijNZpVIOGUTqzM4U55sdsCcZUluWM6x4HSOdw5F5Utxfp1wOjD/v92Lrax0hjiX DResHSt48q+8FrZzY+AUbkUS+Jm34qjswdrgsC5uxeVcLkBgWLmov2kMaMROT0YmFY6A3m1S P/kXmHDXxhe23gKb3dgwxUTpENDBGcfEzrzilWueOeUWiOcWuFOed/C3SyijBx3Av/lbCsHU Vx6pMycNTdzU1BuAroB+Y3mNEuW56Yd44jlInzG2UOwt9XjjdKkJZ1g0P9dwptwLEgTEd3Fo UdhAQyRXGYO8oROiuh+RZ1lXp6AQ4ZjoyH8WLfTLf5g1EKCTc4C1sy1vQSdzIRu3rBIjAvnC tGZADei1IExLqB3uzXKzZ1BZ+Z8hnt2og9hb7H0y8diYfEk2w3R7wEr+Ehk5NQsT2MPI2QBd wEv1/Aj1DgUHZAHzG1QN9S8wNWQ6K9DqHZTBnI1hUlkp22zCSHK/6FwUCuYp1zcAEQEAAc0j UGFvbG8gQm9uemluaSA8cGJvbnppbmlAcmVkaGF0LmNvbT7CwU0EEwECACMFAlRCcBICGwMH CwkIBwMCAQYVCAIJCgsEFgIDAQIeAQIXgAAKCRB+FRAMzTZpsbceDp9IIN6BIA0Ol7MoB15E 11kRz/ewzryFY54tQlMnd4xxfH8MTQ/mm9I482YoSwPMdcWFAKnUX6Yo30tbLiNB8hzaHeRj jx12K+ptqYbg+cevgOtbLAlL9kNgLLcsGqC2829jBCUTVeMSZDrzS97ole/YEez2qFpPnTV0 VrRWClWVfYh+JfzpXmgyhbkuwUxNFk421s4Ajp3d8nPPFUGgBG5HOxzkAm7xb1cjAuJ+oi/K CHfkuN+fLZl/u3E/fw7vvOESApLU5o0icVXeakfSz0LsygEnekDbxPnE5af/9FEkXJD5EoYG SEahaEtgNrR4qsyxyAGYgZlS70vkSSYJ+iT2rrwEiDlo31MzRo6Ba2FfHBSJ7lcYdPT7bbk9 AO3hlNMhNdUhoQv7M5HsnqZ6unvSHOKmReNaS9egAGdRN0/GPDWr9wroyJ65ZNQsHl9nXBqE AukZNr5oJO5vxrYiAuuTSd6UI/xFkjtkzltG3mw5ao2bBpk/V/YuePrJsnPFHG7NhizrxttB nTuOSCMo45pfHQ+XYd5K1+Cv/NzZFNWscm5htJ0HznY+oOsZvHTyGz3v91pn51dkRYN0otqr bQ4tlFFuVjArBZcapSIe6NV8C4cEiSTOwE0EVEJx7gEIAMeHcVzuv2bp9HlWDp6+RkZe+vtl KwAHplb/WH59j2wyG8V6i33+6MlSSJMOFnYUCCL77bucx9uImI5nX24PIlqT+zasVEEVGSRF m8dgkcJDB7Tps0IkNrUi4yof3B3shR+vMY3i3Ip0e41zKx0CvlAhMOo6otaHmcxr35sWq1Jk tLkbn3wG+fPQCVudJJECvVQ//UAthSSEklA50QtD2sBkmQ14ZryEyTHQ+E42K3j2IUmOLriF dNr9NvE1QGmGyIcbw2NIVEBOK/GWxkS5+dmxM2iD4Jdaf2nSn3jlHjEXoPwpMs0KZsgdU0pP JQzMUMwmB1wM8JxovFlPYrhNT9MAEQEAAcLBMwQYAQIACQUCVEJx7gIbDAAKCRB+FRAMzTZp sadRDqCctLmYICZu4GSnie4lKXl+HqlLanpVMOoFNnWs9oRP47MbE2wv8OaYh5pNR9VVgyhD OG0AU7oidG36OeUlrFDTfnPYYSF/mPCxHttosyt8O5kabxnIPv2URuAxDByz+iVbL+RjKaGM GDph56ZTswlx75nZVtIukqzLAQ5fa8OALSGum0cFi4ptZUOhDNz1onz61klD6z3MODi0sBZN Aj6guB2L/+2ZwElZEeRBERRd/uommlYuToAXfNRdUwrwl9gRMiA0WSyTb190zneRRDfpSK5d usXnM/O+kr3Dm+Ui+UioPf6wgbn3T0o6I5BhVhs4h4hWmIW7iNhPjX1iybXfmb1gAFfjtHfL xRUr64svXpyfJMScIQtBAm0ihWPltXkyITA92ngCmPdHa6M1hMh4RDX+Jf1fiWubzp1voAg0 JBrdmNZSQDz0iKmSrx8xkoXYfA3bgtFN8WJH2xgFL28XnqY4M6dLhJwV3z08tPSRqYFm4NMP dRsn0/7oymhneL8RthIvjDDQ5ktUjMe8LtHr70OZE/TT88qvEdhiIVUogHdo4qBrk41+gGQh b906Dudw5YhTJFU3nC6bbF2nrLlB4C/XSiH76ZvqzV0Z/cAMBo5NF/w= In-Reply-To: <20251110180131.28264-3-chang.seok.bae@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 11/10/25 19:01, Chang S. Bae wrote: > Refactor the GPR accessors to introduce internal helpers to distinguish > between legacy and extended registers. > > x86 CPUs introduce additional GPRs, but those registers will initially > remain unused in the kernel and will not be saved in KVM register cache > on every VM exit. Guest states are expected to remain live in hardware > registers. > > This abstraction layer centralizes the selection of access methods, > providing a unified interface. For now, the EGPR accessors are > placeholders to be implemented later. > > Signed-off-by: Chang S. Bae > --- > arch/x86/include/asm/kvm_host.h | 18 ++++++++++++ > arch/x86/include/asm/kvm_vcpu_regs.h | 16 ++++++++++ > arch/x86/kvm/fpu.h | 6 ++++ > arch/x86/kvm/x86.h | 44 ++++++++++++++++++++++++++-- > 4 files changed, 82 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h > index 48598d017d6f..940f83c121cf 100644 > --- a/arch/x86/include/asm/kvm_host.h > +++ b/arch/x86/include/asm/kvm_host.h > @@ -212,6 +212,24 @@ enum { > VCPU_SREG_GS, > VCPU_SREG_TR, > VCPU_SREG_LDTR, > +#ifdef CONFIG_X86_64 > + VCPU_XREG_R16 = __VCPU_XREG_R16, > + VCPU_XREG_R17 = __VCPU_XREG_R17, > + VCPU_XREG_R18 = __VCPU_XREG_R18, > + VCPU_XREG_R19 = __VCPU_XREG_R19, > + VCPU_XREG_R20 = __VCPU_XREG_R20, > + VCPU_XREG_R21 = __VCPU_XREG_R21, > + VCPU_XREG_R22 = __VCPU_XREG_R22, > + VCPU_XREG_R23 = __VCPU_XREG_R23, > + VCPU_XREG_R24 = __VCPU_XREG_R24, > + VCPU_XREG_R25 = __VCPU_XREG_R25, > + VCPU_XREG_R26 = __VCPU_XREG_R26, > + VCPU_XREG_R27 = __VCPU_XREG_R27, > + VCPU_XREG_R28 = __VCPU_XREG_R28, > + VCPU_XREG_R29 = __VCPU_XREG_R29, > + VCPU_XREG_R30 = __VCPU_XREG_R30, > + VCPU_XREG_R31 = __VCPU_XREG_R31, > +#endif > }; > > enum exit_fastpath_completion { > diff --git a/arch/x86/include/asm/kvm_vcpu_regs.h b/arch/x86/include/asm/kvm_vcpu_regs.h > index 1af2cb59233b..dd0cc171f405 100644 > --- a/arch/x86/include/asm/kvm_vcpu_regs.h > +++ b/arch/x86/include/asm/kvm_vcpu_regs.h > @@ -20,6 +20,22 @@ > #define __VCPU_REGS_R13 13 > #define __VCPU_REGS_R14 14 > #define __VCPU_REGS_R15 15 > +#define __VCPU_XREG_R16 16 > +#define __VCPU_XREG_R17 17 > +#define __VCPU_XREG_R18 18 > +#define __VCPU_XREG_R19 19 > +#define __VCPU_XREG_R20 20 > +#define __VCPU_XREG_R21 21 > +#define __VCPU_XREG_R22 22 > +#define __VCPU_XREG_R23 23 > +#define __VCPU_XREG_R24 24 > +#define __VCPU_XREG_R25 25 > +#define __VCPU_XREG_R26 26 > +#define __VCPU_XREG_R27 27 > +#define __VCPU_XREG_R28 28 > +#define __VCPU_XREG_R29 29 > +#define __VCPU_XREG_R30 30 > +#define __VCPU_XREG_R31 31 > #endif > > #endif /* _ASM_X86_KVM_VCPU_REGS_H */ > diff --git a/arch/x86/kvm/fpu.h b/arch/x86/kvm/fpu.h > index 3ba12888bf66..159239b3a651 100644 > --- a/arch/x86/kvm/fpu.h > +++ b/arch/x86/kvm/fpu.h > @@ -4,6 +4,7 @@ > #define __KVM_FPU_H_ > > #include > +#include > > typedef u32 __attribute__((vector_size(16))) sse128_t; > #define __sse128_u union { sse128_t vec; u64 as_u64[2]; u32 as_u32[4]; } > @@ -137,4 +138,9 @@ static inline void kvm_write_mmx_reg(int reg, const u64 *data) > kvm_fpu_put(); > } > > +#ifdef CONFIG_X86_64 > +static inline unsigned long kvm_read_egpr(int reg) { return 0; } > +static inline void kvm_write_egpr(int reg, unsigned long data) { } Do not inline these, they're quite large. Leave them in x86.c. Also please add a KVM_APX Kconfig symbol and add "select KVM_APX if X86_64" to KVM_INTEL. This way, AMD and 32-bit use the same logic to elide all the EGPR code. Paolo > +#endif > + > #endif > diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h > index 4edadd64d3d5..74ae8f12b5a1 100644 > --- a/arch/x86/kvm/x86.h > +++ b/arch/x86/kvm/x86.h > @@ -400,9 +400,49 @@ static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa) > return false; > } > > +#ifdef CONFIG_X86_64 > +static inline unsigned long _kvm_gpr_read(struct kvm_vcpu *vcpu, int reg) > +{ > + switch (reg) { > + case VCPU_REGS_RAX ... VCPU_REGS_R15: > + return kvm_register_read_raw(vcpu, reg); > + case VCPU_XREG_R16 ... VCPU_XREG_R31: > + return kvm_read_egpr(reg); > + default: > + WARN_ON_ONCE(1); > + } > + > + return 0; > +} > + > +static inline void _kvm_gpr_write(struct kvm_vcpu *vcpu, int reg, unsigned long val) > +{ > + switch (reg) { > + case VCPU_REGS_RAX ... VCPU_REGS_R15: > + kvm_register_write_raw(vcpu, reg, val); > + break; > + case VCPU_XREG_R16 ... VCPU_XREG_R31: > + kvm_write_egpr(reg, val); > + break; > + default: > + WARN_ON_ONCE(1); > + } > +} > +#else > +static inline unsigned long _kvm_gpr_read(struct kvm_vcpu *vcpu, int reg) > +{ > + return kvm_register_read_raw(vcpu, reg); > +} > + > +static inline void _kvm_gpr_write(struct kvm_vcpu *vcpu, int reg, unsigned long val) > +{ > + kvm_register_write_raw(vcpu, reg, val); > +} > +#endif > + > static inline unsigned long kvm_gpr_read(struct kvm_vcpu *vcpu, int reg) > { > - unsigned long val = kvm_register_read_raw(vcpu, reg); > + unsigned long val = _kvm_gpr_read(vcpu, reg); > > return is_64_bit_mode(vcpu) ? val : (u32)val; > } > @@ -411,7 +451,7 @@ static inline void kvm_gpr_write(struct kvm_vcpu *vcpu, int reg, unsigned long v > { > if (!is_64_bit_mode(vcpu)) > val = (u32)val; > - return kvm_register_write_raw(vcpu, reg, val); > + _kvm_gpr_write(vcpu, reg, val); > } > > static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk)