Re:[PATCH v7 4/4] drm/rockchip: vop2: Support setting custom background color

["Andy Yan" <andyshrk@163.com>]

Hello Cristian,

At 2026-02-05 04:02:31, "Cristian Ciocaltea" <cristian.ciocaltea@collabora.com> wrote:
>The Rockchip VOP2 display controller allows configuring the background
>color of each video output port.
>
>Since a previous patch introduced the BACKGROUND_COLOR CRTC property,
>which defaults to solid black, make use of it when programming the
>hardware.
>
>Note the maximum precision allowed by the display controller is 10bpc,
>while the alpha component is not supported, hence ignored.
>
>Tested-by: Diederik de Haas <diederik@cknow-tech.com>
>Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>

   Reviewed-by: Andy Yan <andyshrk@163.com>
>---
> drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 17 ++++++++++++++++-
> drivers/gpu/drm/rockchip/rockchip_drm_vop2.h |  4 ++++
> 2 files changed, 20 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
>index ec3b4fde10db..8f22e90a23dd 100644
>--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
>+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
>@@ -1552,6 +1552,7 @@ static void vop2_post_config(struct drm_crtc *crtc)
> 	struct vop2_video_port *vp = to_vop2_video_port(crtc);
> 	struct vop2 *vop2 = vp->vop2;
> 	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
>+	u64 bgcolor = crtc->state->background_color;
> 	u16 vtotal = mode->crtc_vtotal;
> 	u16 hdisplay = mode->crtc_hdisplay;
> 	u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
>@@ -1597,7 +1598,15 @@ static void vop2_post_config(struct drm_crtc *crtc)
> 		vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO_F1, val);
> 	}
> 
>-	vop2_vp_write(vp, RK3568_VP_DSP_BG, 0);
>+	/*
>+	 * Background color is programmed with 10 bits of precision.
>+	 * Since performance is more important than accuracy here,
>+	 * make use of the DRM_ARGB64_GET*_BPCS() helpers.
>+	 */
>+	val = FIELD_PREP(RK3568_VP_DSP_BG__DSP_BG_RED, DRM_ARGB64_GETR_BPCS(bgcolor, 10));
>+	FIELD_MODIFY(RK3568_VP_DSP_BG__DSP_BG_GREEN, &val, DRM_ARGB64_GETG_BPCS(bgcolor, 10));
>+	FIELD_MODIFY(RK3568_VP_DSP_BG__DSP_BG_BLUE, &val, DRM_ARGB64_GETB_BPCS(bgcolor, 10));
>+	vop2_vp_write(vp, RK3568_VP_DSP_BG, val);
> }
> 
> static int us_to_vertical_line(struct drm_display_mode *mode, int us)
>@@ -1983,6 +1992,10 @@ static int vop2_crtc_state_dump(struct drm_crtc *crtc, struct seq_file *s)
> 		   drm_get_bus_format_name(vcstate->bus_format));
> 	seq_printf(s, "\toutput_mode[%x]", vcstate->output_mode);
> 	seq_printf(s, " color_space[%d]\n", vcstate->color_space);
>+	seq_printf(s, "\tbackground color (10bpc): r=0x%x g=0x%x b=0x%x\n",
>+		   DRM_ARGB64_GETR_BPCS(cstate->background_color, 10),
>+		   DRM_ARGB64_GETG_BPCS(cstate->background_color, 10),
>+		   DRM_ARGB64_GETB_BPCS(cstate->background_color, 10));
> 	seq_printf(s, "    Display mode: %dx%d%s%d\n",
> 		   mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p",
> 		   drm_mode_vrefresh(mode));
>@@ -2472,6 +2485,8 @@ static int vop2_create_crtcs(struct vop2 *vop2)
> 			return dev_err_probe(drm->dev, ret,
> 					     "crtc init for video_port%d failed\n", i);
> 
>+		drm_crtc_attach_background_color_property(&vp->crtc);
>+
> 		drm_crtc_helper_add(&vp->crtc, &vop2_crtc_helper_funcs);
> 		if (vop2->lut_regs) {
> 			const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
>diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
>index 9124191899ba..37722652844a 100644
>--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
>+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
>@@ -658,6 +658,10 @@ enum dst_factor_mode {
> #define RK3588_VP_CLK_CTRL__DCLK_OUT_DIV		GENMASK(3, 2)
> #define RK3588_VP_CLK_CTRL__DCLK_CORE_DIV		GENMASK(1, 0)
> 
>+#define RK3568_VP_DSP_BG__DSP_BG_RED			GENMASK(29, 20)
>+#define RK3568_VP_DSP_BG__DSP_BG_GREEN			GENMASK(19, 10)
>+#define RK3568_VP_DSP_BG__DSP_BG_BLUE			GENMASK(9, 0)
>+
> #define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN		BIT(1)
> #define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN		BIT(0)
> 
>
>-- 
>2.52.0
>