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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: wpuM8WZukss3nvd17gcwYPEcTboLCoNeaGMko2AO4dDPgA5CjVNwWVBW8lbGedu5kcnWZlWRdUmkp/AnNWW83fA4J/M4bSMNVlebX6d6RwdRMdJSpVEaTugFpY0sPjtRQQfRKSTkudg3H6II6FRbu1RNEootA2pDeFqNiXon3THPZLF/o15Rnwz7PwQDhV65U3vNlJM/yj/EN66RdHDOfGKHxvuV+zQGD7H+pZjWsHo0+DsyBBkb1YVmp2PmnWxqICgTURsrxwGTyT1tsJ05uqouoX+XlCEvVpsnxhc348ir38l3CBx75nDnmJx3iqyvDJlYSvAQQiYGGYBBIpi9UI97OjmyojHdigNtgxhiHbjkH8iPX6sLKqgUKA0DSJlp3pM6jFQKUwR+1B924lN1vrYZVBeuABnq2KycyctURGky+KCocCaxilavlNcGlLda X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 10:30:15.7478 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dbcb925a-34af-4eb6-a747-08df1d4b7c81 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000C6192.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6975 Temporary BAR1 access needs a borrow of the GPU-owned BarUser. Store BarUser inline in Gpu and borrow it in BarUserAccess, avoiding a separate allocation and reference counting for these accesses. Update the existing self-test entry points to accept the borrowed interface. No functional change is intended. Cc: Alistair Popple Signed-off-by: Zhi Wang --- drivers/gpu/nova-core/gpu.rs | 21 +++++++++------------ drivers/gpu/nova-core/mm.rs | 5 ++--- drivers/gpu/nova-core/mm/bar_user.rs | 27 ++++++++++++--------------- 3 files changed, 23 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 11d9986c4b19..97b33d4b2631 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -16,7 +16,6 @@ SizeConstants, SZ_4K, // }, - sync::Arc, }; use crate::{ @@ -340,7 +339,8 @@ pub(crate) struct Gpu<'gpu> { /// the GSP is still operational. mm: GpuMm<'gpu>, /// BAR1 user interface for CPU access to GPU virtual memory. - bar_user: Arc>, + #[pin] + bar_user: BarUser<'gpu>, /// GSP and its resources. #[pin] gsp_resources: GspResources<'gpu>, @@ -545,18 +545,15 @@ pub(crate) fn new<'a>( }, // Create BAR1 user interface for CPU access to GPU virtual memory. - bar_user: { + bar_user <- { let pdb_addr = VramAddress::from_raw(gsp_resources.static_info().bar1_pde_base()); let bar1_idx = crate::driver::bar1_resource_index(pdev)?; let bar1_size = pdev.resource_len(bar1_idx)?; - Arc::pin_init( - BarUser::new( - pdb_addr, - gsp_resources.spec.chipset, - bar1_size, - bar1, - )?, - GFP_KERNEL, + BarUser::new( + pdb_addr, + gsp_resources.spec.chipset, + bar1_size, + bar1, )? }, }) @@ -573,7 +570,7 @@ pub(crate) fn run_selftests(self: Pin<&mut Self>, pdev: &pci::Device, mm: &mut GpuMm<'_>, mut usable_fb_regions: impl Iterator>, - bar_user: &Arc>, + bar_user: &bar_user::BarUser<'_>, bar1_pdb: u64, chipset: Chipset, ) -> Result { diff --git a/drivers/gpu/nova-core/mm/bar_user.rs b/drivers/gpu/nova-core/mm/bar_user.rs index cd2d0271e64c..414c69e037ee 100644 --- a/drivers/gpu/nova-core/mm/bar_user.rs +++ b/drivers/gpu/nova-core/mm/bar_user.rs @@ -7,10 +7,7 @@ io::Io, new_mutex, prelude::*, - sync::{ - Arc, - Mutex, // - }, + sync::Mutex, // }; use crate::{ @@ -60,12 +57,12 @@ pub(crate) fn new( } /// Map physical pages to a contiguous BAR1 virtual range. - pub(crate) fn map( - self: &Arc, + pub(crate) fn map<'access>( + &'access self, mm: &mut GpuMm<'_>, pfns: &[Pfn], writable: bool, - ) -> Result> { + ) -> Result> { if pfns.is_empty() { return Err(EINVAL); } @@ -73,21 +70,21 @@ pub(crate) fn map( let mapped = vmm.map_pages(mm, pfns, None, writable)?; Ok(BarUserAccess { - bar_user: self.clone(), + bar_user: self, mapped: Some(mapped), }) } } /// Access object for a mapped BAR1 region. -pub(crate) struct BarUserAccess<'gpu> { - bar_user: Arc>, +pub(crate) struct BarUserAccess<'access, 'gpu> { + bar_user: &'access BarUser<'gpu>, /// Cleared only after PTE invalidation and its TLB flush succeed. mapped: Option, } #[expect(dead_code)] -impl BarUserAccess<'_> { +impl BarUserAccess<'_, '_> { /// Tear down the BAR1 mapping. pub(crate) fn release(mut self, mm: &mut GpuMm<'_>) -> Result { self.unmap(mm) @@ -167,7 +164,7 @@ pub(crate) fn try_write64(&self, value: u64, offset: usize) -> Result { } } -impl Drop for BarUserAccess<'_> { +impl Drop for BarUserAccess<'_, '_> { fn drop(&mut self) { if self.mapped.is_some() { kernel::pr_warn!( @@ -185,10 +182,10 @@ fn drop(&mut self) { /// address space. Uses the `GpuMm`'s buddy allocator to allocate page tables /// and test pages as needed. #[cfg(CONFIG_NOVA_CORE_SELFTESTS)] -pub(crate) fn run_self_test( +pub(super) fn run_self_test( dev: &device::Device, mm: &mut GpuMm<'_>, - bar_user: &Arc>, + bar_user: &BarUser<'_>, bar1_pdb: u64, chipset: Chipset, ) -> Result { @@ -401,7 +398,7 @@ pub(crate) fn run_self_test( drop(vmm); // Test 4: Exercise `BarUser::map()` end-to-end. - let bar_user = Arc::pin_init( + let bar_user = KBox::pin_init( BarUser::new(pdb_addr, chipset, SZ_64K.into_safe_cast(), bar1)?, GFP_KERNEL, )?;