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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af47ff43385sm95492466b.144.2025.07.24.03.53.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 24 Jul 2025 03:53:17 -0700 (PDT) Message-ID: <7d444f4c-fa1f-4436-b93a-f2d2b6d49de2@oss.qualcomm.com> Date: Thu, 24 Jul 2025 12:53:14 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] dt-bindings: clock: qcom: Add SM8750 GPU clocks To: Krzysztof Kozlowski , Konrad Dybcio Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250723-topic-8750_gpucc-v2-0-56c93b84c390@oss.qualcomm.com> <20250723-topic-8750_gpucc-v2-1-56c93b84c390@oss.qualcomm.com> <20250724-blazing-therapeutic-python-1e96ca@kuoka> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250724-blazing-therapeutic-python-1e96ca@kuoka> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI0MDA4MSBTYWx0ZWRfX7MBitrDg+yA/ CFk/S0IVAP0jpSY92aWlc2ZHlrpbijmtoTjWbd0hwcWrPcSAf6esHa1rXkCJsjinrfytlhL7jD7 Di44I56os46kkgbVB2mVbTGZ3NbPsT0NbkqZmnix29pUGFQVUNDKOKja7cvHsCZB+xbMKrwMOKU 6mPl6VQL9I3ykgMl0WSTeGIdX45IKl2tcx0o1hEHc5lhdIQdidsRQrcAaXLkd2t6r3Bdy/fofl8 mBfRjSf0iXBd5183K+vQ+FKlkgUy1gS3YkwS+3OPx2OahAhTDkCcSA6AKKcvez8UuJ8zmJThhqM xqp6CFqKmBdJ4IffPK5gLOBuKnUiAWXgF7vRVIzzwG6kb3Z8a33DHw9h0vxAA/3gyVkzfn9HtEy nBtb/eXCb1ZHIqtSp22JJbt7JEaQtAXVQlf/wA7WBfakyO88wWv0feaVeV91bGd4RosYoLXJ X-Proofpoint-ORIG-GUID: Le8xlJp6G0cYtfXhrJ2tMqTPX-mtdsfZ X-Proofpoint-GUID: Le8xlJp6G0cYtfXhrJ2tMqTPX-mtdsfZ X-Authority-Analysis: v=2.4 cv=IrMecK/g c=1 sm=1 tr=0 ts=688210a2 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=y9Hb3FDJ_D53AYP2N1gA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-24_01,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 clxscore=1015 priorityscore=1501 spamscore=0 mlxscore=0 mlxlogscore=999 phishscore=0 impostorscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507240081 On 7/24/25 10:18 AM, Krzysztof Kozlowski wrote: > On Wed, Jul 23, 2025 at 10:38:48PM +0200, Konrad Dybcio wrote: >> From: Konrad Dybcio >> >> The SM8750 features a "traditional" GPU_CC block, much of which is >> controlled through the GMU microcontroller. Additionally, there's >> an separate GX_CC block, where the GX GDSC is moved. >> >> Add bindings to accommodate for that. >> >> Signed-off-by: Konrad Dybcio >> --- [...] >> +title: Qualcomm Graphics Clock & Reset Controller on SM8750 > > There is no clocks nor resets here. Only power domains. There are clocks and resets in this IP block (inside the register space mentioned in the dt patch/example), but the OS is not supposed to poke at them (it can in theory, but we have a uC - the GMU - doing the same thing so it would be stepping on one another's toes..). Not sure how to express that. I could for example add #define indices in include/dt-bindings, listing out the clocks and never consume them. Does that sound fair? > >> + >> +maintainers: >> + - Konrad Dybcio >> + >> +description: | >> + Qualcomm graphics clock control module provides the clocks, resets and power > > Also confusing. > >> + domains on Qualcomm SoCs. >> + >> + See also: >> + include/dt-bindings/reset/qcom,sm8750-gpucc.h > > reset or clock path? Ugh, clock > >> + >> +properties: >> + compatible: >> + enum: >> + - qcom,sm8750-gxcc >> + >> + reg: >> + maxItems: 1 >> + >> + power-domains: >> + items: >> + - description: GFX voltage rail >> + - description: MX_COLLAPSIBLE voltage rail >> + - description: GPU_CC_CX GDSC >> + >> + '#power-domain-cells': >> + const: 1 >> + >> +required: >> + - compatible >> + - power-domains >> + - '#power-domain-cells' >> + > > You miss ref... or this is a bit confusing. ref to what? qcom,gcc? I specifically omitted it, as that adds requirements which you stated above. Konrad > >> +unevaluatedProperties: false > > additionalProperties instead > >> + >> +examples: >> + - | >> + #include >> + #include >> + >> + soc { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + clock-controller@3d64000 { > > No, clock controllers have clock-cells. This cannot be a clock > controller if it does not have any clocks for anyone to use. > > Best regards, > Krzysztof >