From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5FE2C83F33 for ; Thu, 31 Aug 2023 10:00:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243296AbjHaKAk (ORCPT ); Thu, 31 Aug 2023 06:00:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233881AbjHaKAj (ORCPT ); Thu, 31 Aug 2023 06:00:39 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0EA82CED; Thu, 31 Aug 2023 03:00:35 -0700 (PDT) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37V9GP4v032484; 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Thu, 31 Aug 2023 10:00:29 GMT Received: from [10.218.10.146] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Thu, 31 Aug 2023 03:00:23 -0700 Message-ID: <7d4a2cd5-291c-e058-9834-1d7eaf911821@quicinc.com> Date: Thu, 31 Aug 2023 15:30:19 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH 3/4] dt-bindings: clock: qcom: Add GCC clocks for SM4450 Content-Language: en-US To: Krzysztof Kozlowski , Andy Gross , Konrad Dybcio , "Michael Turquette" , Stephen Boyd , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Taniya Das , Imran Shaik , Jagadeesh Kona CC: , , , References: <20230824173410.550126-1-quic_ajipan@quicinc.com> <20230824173410.550126-4-quic_ajipan@quicinc.com> <161de126-87b0-3440-8517-330b529c3fb6@linaro.org> From: Ajit Pandey In-Reply-To: <161de126-87b0-3440-8517-330b529c3fb6@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: gl8gxOXJflGu-4r4GQnPBpF3UPZ9ZV9Z X-Proofpoint-GUID: gl8gxOXJflGu-4r4GQnPBpF3UPZ9ZV9Z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-31_07,2023-08-29_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 bulkscore=0 spamscore=0 mlxlogscore=999 adultscore=0 malwarescore=0 priorityscore=1501 clxscore=1011 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2308310088 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/24/2023 11:40 PM, Krzysztof Kozlowski wrote: > On 24/08/2023 19:34, Ajit Pandey wrote: >> Add support for qcom global clock controller bindings for SM4450 platform. >> >> Signed-off-by: Ajit Pandey >> --- >> .../bindings/clock/qcom,sm4450-gcc.yaml | 54 +++++ >> include/dt-bindings/clock/qcom,sm4450-gcc.h | 197 ++++++++++++++++++ >> 2 files changed, 251 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml >> create mode 100644 include/dt-bindings/clock/qcom,sm4450-gcc.h >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml >> new file mode 100644 >> index 000000000000..8c767bdf7f9d >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml >> @@ -0,0 +1,54 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/qcom,sm4450-gcc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Global Clock & Reset Controller on SM4450 >> + >> +maintainers: >> + - Ajit Pandey >> + - Taniya Das >> + >> +description: | >> + Qualcomm global clock control module provides the clocks, resets and power >> + domains on SM4450 >> + >> + See also:: include/dt-bindings/clock/qcom,sm4450-gcc.h >> + >> +properties: >> + compatible: >> + const: qcom,sm4450-gcc >> + >> + clocks: >> + items: >> + - description: Board XO source >> + - description: Sleep clock source >> + - description: UFS Phy Rx symbol 0 clock source (Optional clock) >> + - description: UFS Phy Rx symbol 1 clock source (Optional clock) >> + - description: UFS Phy Tx symbol 0 clock source (Optional clock) >> + - description: USB3 Phy wrapper pipe clock source (Optional clock) > > I doubt that these are really optional clocks. They are set as parents > of your clocks in the controller, so if these clocks are physically > missing, how does the clock controller work? > > > Best regards, > Krzysztof > Yeah, if these optional clocks are missing, few dependent child clocks functionality (UFS/USB) will not work and clock controller will work with limited functionality, but I agree that the tag "Optional Clock" is bit confusing here and will remove this in next patch series. -- Thanks, and Regards Ajit