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Mon, 28 Sep 2026 11:04:45 +0200 Message-ID: <7d8ee07c-14a5-429d-8c97-6c4ded486f12@foss.st.com> Date: Mon, 28 Sep 2026 11:04:44 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 06/10] arm64: dts: st: Add SDMMC2 and SDMMC3 nodes on stm32mp251 To: Marek Vasut , CC: Bartosz Golaszewski , Conor Dooley , Krzysztof Kozlowski , Linus Walleij , Rob Herring , , , , , References: <20260711210131.236025-1-marex@nabladev.com> <20260711210131.236025-7-marex@nabladev.com> Content-Language: en-US From: Alexandre TORGUE In-Reply-To: <20260711210131.236025-7-marex@nabladev.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: ENXCAS1NODE2.st.com (10.75.128.138) To STKDAG1NODE2.st.com (10.75.128.133) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AMS1EPF0000008D:EE_|AS8PR10MB7729:EE_ X-MS-Office365-Filtering-Correlation-Id: 98b9d952-0774-47b7-4fc6-08df1d3f8b69 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|82310400026|376014|7416014|36860700016|1800799024|4143699003|22082099003|18002099003|10067099003|11063799006|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: R0s5Qjp2v+i+hxXQ5GEJGZwbhHMxx2Jk2/+NYlMXHx/lqINv3jayLIFHMMl0/s8tu3udgCvzSD34szZ71EETI5sf5oB/ypsrAfx/T7tg/a1AZ0fHtotNA3KyOvDnulXGEZvryQGFldp0A9mHksGW3Oj8YVR9wKR4QrfnuY2BVTEbw9M3kOGbnHXlbU74t2Il84lRkdjACpBAnW5hOVc2VP3LzLPUexXdIBzIh7neQNghm5pcoT3aZNN2TA85dsgNfAI65MoWSvrhqWiMyQRsMoHkXlYbYXczhLh3L6UsD8NF8NkkInxYCBPiyROSAHqv1fpraGSSu3+oq0/ep+jRFwStfp2A+rlIOAMrGQtMUdL45Wtx+4JgdLd1HrE+XeiElnmeiR1xu8e1gaUTlbp2vJNzBSbH/ClTkBFDdmGvSez0UbK5ZQs68MxpMukX3NsW X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 09:04:46.8078 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 98b9d952-0774-47b7-4fc6-08df1d3f8b69 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.60];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: AMS1EPF0000008D.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR10MB7729 Hi Marek On 7/11/26 22:59, Marek Vasut wrote: > Add DT nodes for the remaining SDMMC controllers 2 and 3. > > Signed-off-by: Marek Vasut > --- > Cc: Alexandre Torgue > Cc: Bartosz Golaszewski > Cc: Conor Dooley > Cc: Krzysztof Kozlowski > Cc: Linus Walleij > Cc: Rob Herring > Cc: devicetree@vger.kernel.org > Cc: kernel@dh-electronics.com > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-gpio@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: linux-stm32@st-md-mailman.stormreply.com > --- > arch/arm64/boot/dts/st/stm32mp251.dtsi | 30 ++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi > index 66f3f83b8731f..6e985f115b195 100644 > --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi > +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi > @@ -1667,6 +1667,36 @@ sdmmc1: mmc@48220000 { > status = "disabled"; > }; > > + sdmmc2: mmc@48230000 { > + compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; > + arm,primecell-periphid = <0x00353180>; > + reg = <0x48230000 0x400>, <0x44230800 0x8>; > + interrupts = ; > + clocks = <&rcc CK_KER_SDMMC2>; > + clock-names = "apb_pclk"; > + resets = <&rcc SDMMC2_R>; > + cap-sd-highspeed; > + cap-mmc-highspeed; > + max-frequency = <166000000>; I merged some weeks ago a patch introducing SDMCC2. max-freq is 120000000. I'll keep this patch adding SDMMC3, and increasing SDMMC2 max freq. > + access-controllers = <&rifsc 77>; > + status = "disabled"; > + }; > + > + sdmmc3: mmc@48240000 { > + compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; > + arm,primecell-periphid = <0x00353180>; > + reg = <0x48240000 0x400>, <0x44230c00 0x8>; > + interrupts = ; > + clocks = <&rcc CK_KER_SDMMC3>; > + clock-names = "apb_pclk"; > + resets = <&rcc SDMMC3_R>; > + cap-sd-highspeed; > + cap-mmc-highspeed; > + max-frequency = <166000000>; > + access-controllers = <&rifsc 78>; > + status = "disabled"; > + }; > + > ethernet1: ethernet@482c0000 { > compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; > reg = <0x482c0000 0x4000>;