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Mon, 11 Aug 2025 22:07:10 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEUuQTvbkjznzZD3wAoSWPaV/NV4ZMjR4FA8Z5+ChKoQlXLWNgp3NjNrHW6g0TBMCJaplmSmA== X-Received: by 2002:a17:90a:ca96:b0:31e:c95a:cef8 with SMTP id 98e67ed59e1d1-321c0ae441bmr1689037a91.32.1754975229729; Mon, 11 Aug 2025 22:07:09 -0700 (PDT) Received: from [10.217.217.159] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-321c2be2c2csm735782a91.12.2025.08.11.22.07.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Aug 2025 22:07:09 -0700 (PDT) Message-ID: <7da20363-7b7c-4b98-9068-d82a186170fd@oss.qualcomm.com> Date: Tue, 12 Aug 2025 10:37:04 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] dt-bindings: clock: dispcc-sc7280: Add display resets To: Bjorn Andersson , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250811-sc7280-mdss-reset-v1-0-83ceff1d48de@oss.qualcomm.com> <20250811-sc7280-mdss-reset-v1-1-83ceff1d48de@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: <20250811-sc7280-mdss-reset-v1-1-83ceff1d48de@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=IuYecK/g c=1 sm=1 tr=0 ts=689acbff cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=C2TcYtzuST-dhkRVSHAA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-ORIG-GUID: mN7W5QTfx4HO5BhQlXbCCZr1AV4-76Hk X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA5MDAyNSBTYWx0ZWRfX048mIqh4NaZb v9amDIE1NO1tDomRD+OvkmFjSWCEFTT+5gxsa3LSIxn4TvLJ/0wQy2YwqNnlCEM7cN1dnRuSnJr uH80xdPVIqHLQcgtSc8Ibb2HgniKGtin3oIXHSq59QG0dFPX5Yg6iu79LH2mvo2f6yc3ZTJcach GvimLLizc2/WCuuqh8e+GhCkEG7yi1b9oM9LtbnrB2/fjBiB6UbFy5G29nfh1Gw4w31OsdI+q3t 2aW6VQbLZSjbIdukxfieIib+pTO4mtv9aiu8x8vMi0gYk72cE9/fyLlGrvNluyjjmJzFl7iAbcu F4A4TqvcnZpqGC/F+5pfz0hWf/YzxUk/2QHw+dCCEETRKBfHBYgrYnGT1bcI4juqOd/0m0QqTuB hDy6Vbsa X-Proofpoint-GUID: mN7W5QTfx4HO5BhQlXbCCZr1AV4-76Hk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_01,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 spamscore=0 priorityscore=1501 adultscore=0 clxscore=1015 phishscore=0 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508090025 On 8/12/2025 8:41 AM, Bjorn Andersson wrote: > Like other platforms the sc7280 display clock controller provides a > couple of resets, add the defines to allow referring to them. > > Signed-off-by: Bjorn Andersson > --- > include/dt-bindings/clock/qcom,dispcc-sc7280.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/include/dt-bindings/clock/qcom,dispcc-sc7280.h b/include/dt-bindings/clock/qcom,dispcc-sc7280.h > index a4a692c20acfc954251fd1a1a59239ac62b20015..9f113f346be80b8a7815ffb17a6a6ce5e008f663 100644 > --- a/include/dt-bindings/clock/qcom,dispcc-sc7280.h > +++ b/include/dt-bindings/clock/qcom,dispcc-sc7280.h > @@ -52,4 +52,8 @@ > /* DISP_CC power domains */ > #define DISP_CC_MDSS_CORE_GDSC 0 > > +/* DISPCC resets */ > +#define DISP_CC_MDSS_CORE_BCR 0 > +#define DISP_CC_MDSS_RSCC_BCR 1 > + > #endif > Reviewed-by: Taniya Das -- Thanks, Taniya Das