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Sat, 21 Feb 2026 10:22:47 -0800 (PST) X-Received: by 2002:a17:902:e542:b0:2aa:ecec:a43d with SMTP id d9443c01a7336-2ad744a0062mr42498465ad.21.1771698166964; Sat, 21 Feb 2026 10:22:46 -0800 (PST) Received: from [192.168.1.11] ([106.222.231.179]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad7504379csm25510135ad.83.2026.02.21.10.22.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 21 Feb 2026 10:22:46 -0800 (PST) Message-ID: <7dbc0e99-cffb-403a-be7a-27d1b47712fd@oss.qualcomm.com> Date: Sat, 21 Feb 2026 23:52:40 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes To: Taniya Das , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio References: <20260220-gpucc_sm8750_v2-v3-0-6c5408564c3c@oss.qualcomm.com> <20260220-gpucc_sm8750_v2-v3-3-6c5408564c3c@oss.qualcomm.com> From: Akhil P Oommen Content-Language: en-US In-Reply-To: <20260220-gpucc_sm8750_v2-v3-3-6c5408564c3c@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: O8G3YwxYB_bWbbmVxSsRPieGgPt7rqj- X-Authority-Analysis: v=2.4 cv=cJftc1eN c=1 sm=1 tr=0 ts=6999f7f8 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nGub0OD3bIp9TpioTFTxbA==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=_nDl3K6yXJEX041QHmYA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-ORIG-GUID: O8G3YwxYB_bWbbmVxSsRPieGgPt7rqj- X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjIxMDE3NSBTYWx0ZWRfXxvxVg9AXN+iv cNVPTBQkKTYUi3QqYs/Yy/XjMD/Rdxvd8oDDNYZNY/ot0axjOGtaPJ/KPUFBUJocurT5J2Jr7cn P2iH7r1+J+UlygGdU4XTp85JIiApBq5IdQFpXzCdHlzR6W9JaqghEdm88Q9Df3II+wMTAxDvzIZ qrUvuxRLICblkkGxwtPNL8he8WVKCAbf2qWouai0SFTLtsS2OqP3aDZjsKVNA7gLvyIocHnTz2Z Onf7iq8MhUrL3hNP2+VLF4PmQZ/s6lQefJBVOJenmg6LWF3fj6vtVW02mSRIeF/nb6HebMjCIaM 23Afi7vbkvMPKldoAJ9+FLTI59gpshPdY/EWjv01xV5bESlk9d8LJgIeoo+AFGEQnOS1quaVvlv YhlXFAQs/9g5MvWSF0a7N0heW0NOnoM482pYxSrLi8XAldmZdr68RDE8W6j/7ELfmvktJG7oNC1 rjPqn4cCG1pHAyLIUqQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-21_05,2026-02-20_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 clxscore=1015 malwarescore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602210175 On 2/20/2026 11:24 AM, Taniya Das wrote: > From: Konrad Dybcio > > Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this > is simply a separate block housing the GX GDSC) nodes, required to > power up the graphics-related hardware. > > Make use of it by enabling the associated IOMMU as well. The GPU itself > needs some more work and will be enabled later. > > Signed-off-by: Konrad Dybcio > Co-developed-by: Taniya Das > Signed-off-by: Taniya Das > --- > arch/arm64/boot/dts/qcom/sm8750.dtsi | 64 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 64 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi > index f56b1f889b857a28859910f5c4465c8ce3473b00..0cc931d0bc96e9563ce4e7989ecd4ba50bd424f8 100644 > --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi > @@ -4,7 +4,9 @@ > */ > > #include > +#include > #include > +#include > #include > #include > #include > @@ -3001,6 +3003,30 @@ videocc: clock-controller@aaf0000 { > #power-domain-cells = <1>; > }; > > + gxclkctl: clock-controller@3d64000 { > + compatible = "qcom,sm8750-gxclkctl"; > + reg = <0x0 0x03d64000 0x0 0x6000>; > + > + power-domains = <&rpmhpd RPMHPD_GFX>, > + <&rpmhpd RPMHPD_GMXC>, > + <&gpucc GPU_CC_CX_GDSC>; > + > + #power-domain-cells = <1>; > + }; > + > + gpucc: clock-controller@3d90000 { > + compatible = "qcom,sm8750-gpucc"; > + reg = <0x0 0x03d90000 0x0 0x9800>; > + > + clocks = <&bi_tcxo_div2>, > + <&gcc GCC_GPU_GPLL0_CLK_SRC>, > + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; > + > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; On Pakala and newer GPUs, we need to scale GMU (which is connected to the CX GDSC) freq. Is this DT description sufficient to allow scaling of GMU OPP? -Akhil. > + }; > + > pdc: interrupt-controller@b220000 { > compatible = "qcom,sm8750-pdc", "qcom,pdc"; > reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; > @@ -4515,6 +4541,44 @@ tpdm_swao_out: endpoint { > }; > }; > > + adreno_smmu: iommu@3da0000 { > + compatible = "qcom,sm8750-smmu-500", "qcom,adreno-smmu", > + "qcom,smmu-500", "arm,mmu-500"; > + reg = <0x0 0x03da0000 0x0 0x40000>; > + #iommu-cells = <2>; > + #global-interrupts = <1>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; > + clock-names = "hlos"; > + power-domains = <&gpucc GPU_CC_CX_GDSC>; > + dma-coherent; > + }; > + > apps_smmu: iommu@15000000 { > compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500"; > reg = <0x0 0x15000000 0x0 0x100000>; >