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[83.9.1.44]) by smtp.gmail.com with ESMTPSA id v7-20020a056512348700b004a2511b8224sm413426lfr.103.2022.12.13.07.34.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 13 Dec 2022 07:34:58 -0800 (PST) Message-ID: <7df05698-0aef-7c9c-4577-3d400c631da8@linaro.org> Date: Tue, 13 Dec 2022 16:34:56 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.1 Subject: Re: [PATCH 4/7] drm/msm/a6xx: Add support for A650 speed binning Content-Language: en-US To: Doug Anderson Cc: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org, marijn.suijten@somainline.org, Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Akhil P Oommen , Chia-I Wu , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20221213002423.259039-1-konrad.dybcio@linaro.org> <20221213002423.259039-5-konrad.dybcio@linaro.org> From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 13.12.2022 16:23, Doug Anderson wrote: > Hi, > > On Mon, Dec 12, 2022 at 4:24 PM Konrad Dybcio wrote: >> >> Add support for matching QFPROM fuse values to get the correct speed bin >> on A650 (SM8250) GPUs. >> >> Signed-off-by: Konrad Dybcio >> --- >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 17 +++++++++++++++++ >> 1 file changed, 17 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> index 2c1630f0c04c..f139ec57c32d 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> @@ -1887,6 +1887,20 @@ static u32 a640_get_speed_bin(u32 fuse) >> return UINT_MAX; >> } >> >> +static u32 a650_get_speed_bin(u32 fuse) >> +{ >> + if (fuse == 0) >> + return 0; >> + else if (fuse == 1) >> + return 1; >> + else if (fuse == 2) >> + return 2; >> + else if (fuse == 3) >> + return 3; >> + >> + return UINT_MAX; > > Unlike some of the other functions, you don't need any complexity. Just do: > > if (fuse <= 3) > return fuse; > > return UINT_MAX; I'd prefer to keep it open-coded, it's just 8150 and 8250 that have these simple fuse values, other SoCs have random numbers (check A618/ 619 above, for example).. Plus the returned values might as well be made-up, as it's just for opp matching. > > > I'd also suggest that perhaps "UINT_MAX" isn't exactly the right > return value for when we have an unrecognized fuse. The return type > for the function is "u32" which is a fixed size type. UINT_MAX, > however, is a type that is automatically sized by the compiler. Though > it's unlikely, theoretically a compiler could be configured such that > "unsigned int" was something other than 32 bits. Ideally either the > return type would be changed to "unsigned int" or you'd return > 0xffffffff as the sentinel value. That's out of the scope of this patch, as it concerns all the speedbin-supported GPUs. The returned value feeds 1< > -Doug