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From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Jason-JH Lin <jason-jh.lin@mediatek.com>,
	Chun-Kuang Hu <chunkuang.hu@kernel.org>
Cc: Nancy Lin <nancy.lin@mediatek.com>,
	Singo Chang <singo.chang@mediatek.com>,
	Yongqiang Niu <yongqiang.niu@mediatek.com>,
	Sirius Wang <sirius.wang@mediatek.com>,
	Xavier Chang <xavier.chang@mediatek.com>,
	Fei Shao <fshao@chromium.org>, Chen-yu Tsai <wenst@chromium.org>,
	Pin-yen Lin <treapking@chromium.org>,
	dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	linux-mediatek@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH v2] mailbox: mtk-cmdq: Refine GCE_GCTL_VALUE setting
Date: Mon, 24 Feb 2025 15:01:00 +0100	[thread overview]
Message-ID: <7dfa6548-c2ad-4492-832d-87dea1ececf5@collabora.com> (raw)
In-Reply-To: <20250224105414.3576243-1-jason-jh.lin@mediatek.com>

Il 24/02/25 11:50, Jason-JH Lin ha scritto:
> Add cmdq_gctl_value_toggle() to configure GCE_CTRL_BY_SW and GCE_DDR_EN
> together in the same GCE_GCTL_VALUE register.
> 
> For the SoCs whose GCE is located in MMINFRA and uses MMINFRA_AO power,
> this allows it to be written without enabling the clocks. Otherwise, all
> GCE registers should be written after the GCE clocks are enabled.
> Move this function into cmdq_runtime_resume() and cmdq_runtime_suspend()
> to ensure it is called when the GCE clock is enabled.
> 
> Fixes: 7abd037aa581 ("mailbox: mtk-cmdq: add gce ddr enable support flow")
> Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>



  reply	other threads:[~2025-02-24 14:01 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-24 10:50 Jason-JH Lin
2025-02-24 14:01 ` AngeloGioacchino Del Regno [this message]
2025-02-24 14:02 ` AngeloGioacchino Del Regno
2025-03-06 10:53 ` AngeloGioacchino Del Regno

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