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Tue, 09 Jun 2026 07:07:38 -0700 (PDT) X-Received: by 2002:a05:6102:548c:b0:633:3bf6:977c with SMTP id ada2fe7eead31-719160955fbmr459224137.1.1781014058545; Tue, 09 Jun 2026 07:07:38 -0700 (PDT) Received: from [192.168.120.170] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bf0559eee00sm1064314366b.56.2026.06.09.07.07.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Jun 2026 07:07:37 -0700 (PDT) Message-ID: <7e04a133-05c2-4137-9ac4-c4fd4ecdd505@oss.qualcomm.com> Date: Tue, 9 Jun 2026 16:07:34 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 7/7] arm64: dts: qcom: mahua: Switch pcie5_phy ref clock to RPMH_CXO_CLK To: Krzysztof Kozlowski , Qiang Yu , Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, krishna.chundru@oss.qualcomm.com References: <20260527-tcsr_qref_0527-v4-0-ded83866c9d9@oss.qualcomm.com> <20260527-tcsr_qref_0527-v4-7-ded83866c9d9@oss.qualcomm.com> <245e1e8c-45e4-426d-9c0c-4c2c0952223b@kernel.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <245e1e8c-45e4-426d-9c0c-4c2c0952223b@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: 7JS-G1WFY_fdyM7wEtnIodk3vBcVs9KM X-Authority-Analysis: v=2.4 cv=EI42FVZC c=1 sm=1 tr=0 ts=6a281e2b cx=c_pps a=DUEm7b3gzWu7BqY5nP7+9g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=aQRuXO-KHT3Wpr6myUEA:9 a=QEXdDO2ut3YA:10 a=-aSRE8QhW-JAV6biHavz:22 X-Proofpoint-GUID: 7JS-G1WFY_fdyM7wEtnIodk3vBcVs9KM X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA5MDEzNCBTYWx0ZWRfX8WUrQUh/8Sck jqBaGNpSra3cYDUIUA09llJxpg1Sgj4/p1WTUDoeY1hq5U28UA0yJL7SwTg+yZTrdqJwrix/RST yTEGSlkFHz3RFreZr8QKwMf4PdmDSWayMb+rWDTfr7CFhr1NMbuhQD8h/HnWjrOyA4t8+1y9sK6 B5g4LObS2yxFGCaDq4d+LeQEV/YZ0hPUfHOY0xkqyUgDSAEVVmQn/HKGwWKqRdgYvGd0Lzc5CQ+ qni3L2mcGsYxUhjxpA24ytgQJLz59eYVbWe2KaEcK0+FlDBhBYN1GK3/5zxsVY1CeFkyaV665MT xMZzgY97keILlRPxzcfYLbaqegB/NfcY/cNh7GI2nMQjGNNXRrFp1ceVV7B715IHZlJNeMU7wyE luIZ7xBtws6R9vN3qLS5BUBLTIHvPU/o2sKqFXQPZ9cyOA0VtqpRa7w65dF2V+jBblvH/OAcHjx KmqTcG9+LVBovkc8avQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-09_03,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 adultscore=0 bulkscore=0 phishscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606090134 On 6/9/26 3:55 PM, Krzysztof Kozlowski wrote: > On 09/06/2026 15:06, Konrad Dybcio wrote: >> On 5/28/26 4:29 AM, Qiang Yu wrote: >>> PCIe5 PHY on Mahua gets refclk from CXO0 pad directly, so no QREF >>> clkref_en voting is required. Override the clock list to use RPMH_CXO_CLK >>> directly instead. >> >> This is the last piece of the puzzle that this series is missing. >> There's no QREF clkref_en, but there is a refgen that needs to be >> powered. For PCIe5 on Mahua this would be L2F_E0 (0p9) and L4H_E0 >> (1p2). >> >> I think the easiest (laziest?) solution would be to add dummy clocks >> in the clkref driver and only toggle the required regulators. Another >> option is to defer back to individual drivers (such as PCIe QMPPHY). >> >> I kinda like the "one central node to drive power" approach, but I'm >> not sure others agree, since it stretches truth just a tiny bit >> (although not as much as one would think since there are *some* >> controls for the transparent-to-the-OS hw pieces in these paths still >> in TCSR).. Dmitry, Krzysztof, would you object to that? > > Not sure what you ask here... the tcsr will get the refgen supplies and > that's all what is needed from DT. What I'm saying is that there are always-on clock branches (no register to control them) which go through controllable repeaters (with a reg in tcsr, although we never control them since the reset state is OK) Both the repeaters and the associated refgens need power supplies. My suggestion was to take care of that by adding "fake" clocks. Currently, we have e.g.: &usb_0_qmpphy { vdda-phy-supply = <&vreg_l4h_e0_1p2>; vdda-pll-supply = <&vreg_l3f_e0_0p72>; refgen-supply = <&vreg_l2f_e0_0p82>; // the other 1.2v refgen is missing status = "okay"; }; The refgen supply is deferred to the QMPPHY node itself, and the repeaters on the way are ignored. The "ref" clock points to RPMH_XO. What I'm suggesting is that we add "fake" (i.e. uncontrollable) TCSR clocks, such as the inexistent TCSR_USB4_0_CLKREF_EN, to which we can link the required regulators, both for the repeaters and the refgen source Konrad