From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=192.198.163.10 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793837630; b=vlTDzUBw1LFWmy88U7zaWFFyjrf4g63AsGGbXtdPW2058V7MY2uoWNYBxZqRPMBUYkNB DRZSYszagvOj0QThZv3Gi2RPU1sv2HFvtcUY8MKZtP6dJ+uFJJXKrAd68z9yGBRJ1YO8Z 237OJ5rBoWXtXC/oKwLk0LiJZeMlr93LDu9MyM9kr/onFWtuXR8c82phcIdwYHRVmWDL1 3vpWkL3DgI+eeWF7AZLQZn3H9L9FMmm23MGEGbQKn2aKQ2ltmHbfFgedMznFgbV/tjeWi ewGglQ636IUmDIXXmZGTngRBDF6YFvDKdVFx3fsksURF51mnpzHTRdGltmAfFVF4nLA== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793837630; h=DMARC-Filter:DKIM-Signature:X-CSE-ConnectionGUID:X-CSE-MsgGUID: X-IronPort-AV:X-IronPort-AV:Received:X-CSE-ConnectionGUID: X-CSE-MsgGUID:X-ExtLoop1:X-IronPort-AV:Received:From:To:Cc:Subject: Date:Message-ID:X-Mailer:In-Reply-To:References:MIME-Version: Content-Transfer-Encoding; bh=bets71Z4qg/3bCcSmNWt/iqYs1Ln3QYefkAdCD745uE=; b=ktuv4VeNyhNHgoRE0/dTMLFtQMW03gFdRULqufx55qbtmqD/3AXBs3qlUDkCwGDwXMyF 4849f38s478CJrPybY0wAhlIl5SWtd+3uW2KrW5AWDjh9Lk9wU9VHKQ/3UCcEHB3oqgv+ HYRv5Nr5LX3ifIoBGtNC5a/tqgmGl9xHMTrQueL690Y/pHxmxfmFBGXEWVnxT0ygOf7eK F9kYDHR3PJp/9pWifwhbZgU+PrkI+8ntWw6UAwGvNoWN6hG5Uwq0FSoYJVp+gGKvbmD4O SThu/U1Cc9MdjiFvWZvdcGT+u9/3X5gz65sI68hQetxtFAVuLVH8v/bSqfpvmlwcVrA== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=IgfdxaAU; arc=none smtp.remote-ip=192.198.163.10 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A53ED606A339 for ; Thu, 5 Nov 2026 00:13:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.2 smtp.subspace.kernel.org A53ED606A339 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=IgfdxaAU DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1793837629; x=1825373629; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wbVVW42RyZpXl+ZlnD8pyMLPdDkEzmUisjycwcA4chA=; b=IgfdxaAUoMNAb8qnTUgt1cN+kjHRlXvgSUSu5jxLEw18CGwKmrHSsIqO mHnb5qbHYr6xYbR0/G86BCim9YSdns61c6aee81TTiJNVvIdjhi8W2Tia fwnEloRy3l2IDuSNAjig1rpma81OBfpTUv6oa1hDXVCxLNYxAnsReMtie zFa1K11+JnwEJIgMMMRoU3uYjjMKd8UOzgRk5h8/5EF8/Zw4i6sLnRuom ZWTLHLwmkNbTyupmTklc7Ahu50OG5I4AEzEikXIH4oGJgjwSsmWRPXbzU VzihZMse3wjdhiFD74qglGbkHYB2G34NZhP0+88VdtVFqXBD+1q5rApQI w==; X-CSE-ConnectionGUID: wpEivisMQ+aLUvq4hi6rXw== X-CSE-MsgGUID: 70bQYv3VSNKDLw/My8A0uA== X-IronPort-AV: E=McAfee;i="6800,10657,11956"; a="2512756" X-IronPort-AV: E=Sophos;i="6.27,196,1787036400"; d="scan'208";a="2512756" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2026 16:13:48 -0800 X-CSE-ConnectionGUID: L6xrllTySrSO+icxeDz+Yw== X-CSE-MsgGUID: 0ytzkm6+R5qKjQio+byNcQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,196,1787036400"; d="scan'208";a="7168843" Received: from rchatre-desk1.jf.intel.com ([10.165.154.99]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2026 16:13:48 -0800 From: Reinette Chatre To: tony.luck@intel.com, ben.horgan@arm.com, james.morse@arm.com, Dave.Martin@arm.com, babu.moger@amd.com, bp@alien8.de, tglx@linutronix.de, dave.hansen@linux.intel.com Cc: x86@kernel.org, hpa@zytor.com, fustini@kernel.org, fenghuay@nvidia.com, peternewman@google.com, yu.c.chen@intel.com, linux-kernel@vger.kernel.org, patches@lists.linux.dev, reinette.chatre@intel.com Subject: [PATCH v3 2/5] x86,fs/resctrl: Remove unnecessary non-linear MBA configuration check Date: Wed, 4 Nov 2026 16:13:30 -0800 Message-ID: <7e1aeee81a38a33ca889db68e4c645f935e4e6cd.1793834224.git.reinette.chatre@intel.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: References: X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Writing a bandwidth value from user space is rejected if the MBA resource has non-linear delay values while the architecture indicates (via resctrl_membw::arch_needs_linear) it can only configure resources with linear delay values. Intel indicates this for MBA while AMD and MPAM do not. This check can never fail. No Intel SKU supports non-linear delay values, and the placeholder for such support, rdt_get_mb_table(), is only called during enumeration and always fails. A non-linear Intel MBA resource is thus never marked as capable of allocation, and resctrl never exposes it to user space or attempts to configure it. Every Intel MBA resource capable of allocation has linear delay values, and AMD and MPAM never indicate a need for them. Fail enumeration of a non-linear Intel MBA resource directly to make clear that it is not supported, and remove the check together with the resctrl_membw::arch_needs_linear property it relies on. Keep the informational message printed when such a system is encountered. While moving it, reword it to no longer refer to the removed mapping table, add the missing newline, and label the printed family value "family" instead of "cpu". Signed-off-by: Reinette Chatre Reviewed-by: Chen Yu Reviewed-by: Tony Luck Acked-by: Jinjie Ruan --- Changes since RFC v1: - Fix typo in changelog Changes since RFC v2: - Rework changelog. - Group all r->membw assignments together. Changes since v1: - Keep (and fix) existing pr_info() message if a non-linear platform appears. (Chenyu) - Rework changelog. - Group rdt_resource::membw assignments together. Changes since v2: - Add tags from Chenyu, Jinjie, and Tony. --- arch/x86/kernel/cpu/resctrl/core.c | 42 +++++++----------------------- fs/resctrl/ctrlmondata.c | 8 ------ include/linux/resctrl.h | 2 -- 3 files changed, 10 insertions(+), 42 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index f9677e52790e..f96f7cf255d0 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -181,27 +181,6 @@ static inline void cache_alloc_hsw_probe(void) rdt_alloc_capable = true; } -/* - * rdt_get_mb_table() - get a mapping of bandwidth(b/w) percentage values - * exposed to user interface and the h/w understandable delay values. - * - * The non-linear delay values have the granularity of power of two - * and also the h/w does not guarantee a curve for configured delay - * values vs. actual b/w enforced. - * Hence we need a mapping that is pre calibrated so the user can - * express the memory b/w as a percentage value. - */ -static inline bool rdt_get_mb_table(struct rdt_resource *r) -{ - /* - * There are no Intel SKUs as of now to support non-linear delay. - */ - pr_info("MBA b/w map not implemented for cpu:%d, model:%d", - boot_cpu_data.x86, boot_cpu_data.x86_model); - - return false; -} - static __init bool __get_mem_config_intel(struct rdt_resource *r) { struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); @@ -212,18 +191,18 @@ static __init bool __get_mem_config_intel(struct rdt_resource *r) cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full); hw_res->num_closid = edx.split.cos_max + 1; max_delay = eax.split.max_delay + 1; - r->membw.max_bw = MAX_MBA_BW; - r->membw.arch_needs_linear = true; - if (ecx & MBA_IS_LINEAR) { - r->membw.delay_linear = true; - r->membw.min_bw = MAX_MBA_BW - max_delay; - r->membw.bw_gran = MAX_MBA_BW - max_delay; - } else { - if (!rdt_get_mb_table(r)) - return false; - r->membw.arch_needs_linear = false; + + if (!(ecx & MBA_IS_LINEAR)) { + pr_info("Non-linear MBA delay values not supported for family:%d, model:%d\n", + boot_cpu_data.x86, boot_cpu_data.x86_model); + return false; } + r->membw.delay_linear = true; + r->membw.max_bw = MAX_MBA_BW; + r->membw.min_bw = MAX_MBA_BW - max_delay; + r->membw.bw_gran = MAX_MBA_BW - max_delay; + if (boot_cpu_has(X86_FEATURE_PER_THREAD_MBA)) r->membw.throttle_mode = THREAD_THROTTLE_PER_THREAD; else @@ -255,7 +234,6 @@ static __init bool __rdt_get_mem_config_amd(struct rdt_resource *r) /* AMD does not use delay */ r->membw.delay_linear = false; - r->membw.arch_needs_linear = false; /* * AMD does not use memory delay throttle model to control diff --git a/fs/resctrl/ctrlmondata.c b/fs/resctrl/ctrlmondata.c index cafebdff70dc..4562072b8ba6 100644 --- a/fs/resctrl/ctrlmondata.c +++ b/fs/resctrl/ctrlmondata.c @@ -45,14 +45,6 @@ static bool bw_validate(char *buf, u32 *data, struct rdt_resource *r) int ret; u32 bw; - /* - * Only linear delay values is supported for current Intel SKUs. - */ - if (!r->membw.delay_linear && r->membw.arch_needs_linear) { - rdt_last_cmd_puts("No support for non-linear MB domains\n"); - return false; - } - ret = kstrtou32(buf, 10, &bw); if (ret) { rdt_last_cmd_printf("Invalid MB value %s\n", buf); diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index b63dc62690ca..66dc9813c888 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -249,7 +249,6 @@ enum membw_throttle_mode { * @max_bw: Maximum memory bandwidth value, used as the reset value * @bw_gran: Granularity at which the memory bandwidth is allocated * @delay_linear: True if memory B/W delay is in linear scale - * @arch_needs_linear: True if we can't configure non-linear resources * @throttle_mode: Bandwidth throttling mode when threads request * different memory bandwidths * @mba_sc: True if MBA software controller(mba_sc) is enabled @@ -259,7 +258,6 @@ struct resctrl_membw { u32 max_bw; u32 bw_gran; u32 delay_linear; - bool arch_needs_linear; enum membw_throttle_mode throttle_mode; bool mba_sc; }; -- 2.56.0