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Mon, 2 Feb 2026 02:15:50 -0600 Message-ID: <7e1c38de-c3a8-4275-a9a4-03773ed9dd6e@ti.com> Date: Mon, 2 Feb 2026 13:45:49 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] PCI: dwc: ep: Fix MSI-X configuration to write to correct physical function To: Niklas Cassel CC: , , , , , , , , , , , , , References: <20260202072758.101845-1-a-garg7@ti.com> <20260202072758.101845-2-a-garg7@ti.com> Content-Language: en-US From: Aksh Garg In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F7:EE_|SJ0PR10MB4445:EE_ X-MS-Office365-Filtering-Correlation-Id: aeaa5659-a653-4b1c-3132-08de62334de2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|7416014|1800799024; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: LatVGJy2MKilEYkohGy5PrntbqMuT4/pDk38Wv6GHY0RELt/odcMZBRuuDwOtb1dm6SElO/Lv29nN1kDzmqbeWHs+2VN2OhDRc7Qe6SfCQaNQA7HeCCI2Q5V92mE1x2R0vFesLkx69fTSje2w+ItvG83CcK70SW9/0VpT5bxsS1TTQSQdXjQEAGRo4j2k2x3/1nMB+uQElF9gVoDDWiBuJoMuGfhlJnLAsAZ8IvpFbsu6z4YIh/U1qxI78rPg/fpJURLAHRa2yigaUemZCVfW2o688SzGqqC8j9OKbMJr78c2VmpqNPlEtW1/wwcMhye7+4DkK4KEEzbfSy5pj5xMofRh7PzfV/gC3jMkqYVUiDz4PBq4xHoI2nsxLQMWtYs0arId+FQL8VMpYkBv1FmmlLr1rTX3264FSfy2Sv5w2P2H1nTESytUBX9qqUmTQeE X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2026 08:16:02.1450 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aeaa5659-a653-4b1c-3132-08de62334de2 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F7.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR10MB4445 On 02/02/26 13:27, Niklas Cassel wrote: > On Mon, Feb 02, 2026 at 08:55:52AM +0100, Niklas Cassel wrote: >> On Mon, Feb 02, 2026 at 12:57:57PM +0530, Aksh Garg wrote: >> > The MSI-X configuration code reads from the correct physical function's >> > register space using dw_pcie_ep_readw_dbi(), but writes back only to >> > PF0 using the old dw_pcie_writew_dbi() helper. This causes incorrect >> > MSI-X configuration for other PFs. >> > >> > Fix this by using dw_pcie_ep_writew_dbi() to write to the correct PF's >> > register space, matching the read operation. >> > >> > Fixes: 70fa02ca1446 ("PCI: dwc: Add dw_pcie_ep_{read,write}_dbi[2] helpers") >> > Signed-off-by: Aksh Garg >> > --- >> > drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +- >> > 1 file changed, 1 insertion(+), 1 deletion(-) >> > >> > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c >> > index 7e7844ff0f7e..771241e1a2c9 100644 >> > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c >> > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c >> > @@ -745,7 +745,7 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no, >> > val = dw_pcie_ep_readw_dbi(ep, func_no, reg); >> > val &= ~PCI_MSIX_FLAGS_QSIZE; >> > val |= nr_irqs - 1; /* encoded as N-1 */ >> > - dw_pcie_writew_dbi(pci, reg, val); >> > + dw_pcie_ep_writew_dbi(ep, func_no, reg, val); >> > >> > reg = ep_func->msix_cap + PCI_MSIX_TABLE; >> > val = offset | bir; >> > -- >> > 2.34.1 >> > >> >> Reviewed-by: Niklas Cassel >> >> >> However, please also fix the only remaining place in this file which still >> uses the incorrect dw_pcie_writew_dbi() instead of dw_pcie_ep_writew_dbi() >> >> i.e.: >> dw_pcie_ep_raise_msix_irq_doorbell(). > > Perhaps doorbell is special, and there is only one register for this... > Yes, we have only one doorbell register. > But then, perhaps add a comment why this is the only place that needs > to not supply func_no. However, I think the offset (0x948) of the register is self-explanatory, as after 0x700, we have port logic registers, which are per-device, not per-PF. >