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Wed, 7 Oct 2026 20:52:59 +0000 Received: by hermes--production-ir2-5dd9bf4598-c2rmk (Yahoo Inc. Hermes SMTP Server) with ESMTPA ID 2102fc31c199ea9497d916c954f0569e; Wed, 07 Oct 2026 20:42:38 +0000 (UTC) Message-ID: <7e3518aa-4f99-4aae-bd9b-3984bdc4b548@yahoo.com> Date: Wed, 7 Oct 2026 22:42:36 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH net-next 8/8] net: dsa: realtek: rtl8365mb: re-latch the family D SerDes From: Mieczyslaw Nalewaj To: linusw@kernel.org, alsi@bang-olufsen.dk, andrew@lunn.ch, olteanv@gmail.com, kuba@kernel.org, davem@davemloft.net, edumazet@google.com, pabeni@redhat.com, linux@armlinux.org.uk, luizluca@gmail.com, maxime.chevallier@bootlin.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org References: <84fc7483-b22d-45ea-a3b8-3285dc357265@yahoo.com> Content-Language: pl In-Reply-To: <84fc7483-b22d-45ea-a3b8-3285dc357265@yahoo.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Mailer: WebService/1.1.26668 mail.backend.jedi.jws.acl:role.jedi.acl.token.atz.jws.hermes.yahoo The family D receiver latches on the DISABLE -> HSGMII edge in SDS_MISC rather than on the value, and it will not latch until the MAC at the other end of the trunk has brought its own half of the link up. If it does not latch, the trunk reports 2.5Gbps/Full on both sides but moves no frames: the CPU MAC transmits, the switch CPU port counts no octets, and there are no CRC, alignment or FIFO errors. The two ends can be seconds apart, e.g. on an IPQ5018 board: 5.27 rtl8365mb: configuring for fixed/2500base-x <- pcs_config() 7.72 ipq5018-gmac-dwmac eth0: configuring for fixed/2500base-x 8.02 ipq5018-gmac-dwmac eth0: Link is Up - 2.5Gbps/Full 8.56 SerDes latches pcs_config() runs seconds before the far-end MAC even starts configuring, so a single edge driven from there is not enough: the receiver has nothing to latch onto yet. Neither is pcs_link_up(), which is seconds early for the same reason. phylink does not help either - it never calls rtl8365mb_pcs_get_state() for this port in the first place, since mb->pcs.poll only arms phylink's own poll for in-band links, and this CPU port is a fixed link. There is no local signal that predicts when the far-end MAC will bring up its half of the link (bit 8 of the SDS link-status word does not change ahead of it), so the work cannot wait for it; it can only tell afterwards, from the link-status bit, whether an edge took. Nothing external re-checks this later. So pcs_config() kicks off one attempt, and the work re-arms itself after each edge; the next run checks whether the edge took, rather than waiting on a poll that will not come. Each attempt (park for 20 ms, then restore the target mode) is performed by a short work: sleeping is not permitted in the PCS ops, and the work also serializes against pcs_config() re-runs, which cancel it. Before parking, the work reads the link status itself and does not park if the receiver has already latched, since the condition that queued it may be stale by the time it runs; it then ends the episode instead. Attempts are spaced about 1 s apart and capped at RTL8365MB_D_SDS_RELATCH_MAX_TRIES (15) per fast episode. After the last attempt one more run checks whether it took and only then warns that the SerDes did not latch. The work then keeps driving one edge per RTL8365MB_D_SDS_HEALTHCHECK_INTERVAL, so a far end that comes up late or a link that drops again is recovered without a reconfiguration, at a bounded cost of one 20 ms park per interval. Once the receiver has latched, the work keeps checking the link every 10 s (RTL8365MB_D_SDS_HEALTHCHECK_INTERVAL). If it finds the link down outside a reconfiguration, e.g. after the far end reset its PLL, it logs that and starts a new episode. An episode also starts at every pcs_config(). For family D, pcs_config() keeps the masked update of SDS_MISC and saves the value it wrote as the target the work restores. The work parks and restores with masked updates over the same fields, so other bits are never touched. The work now accesses the shared SDS_INDACS ADR/CMD/DATA window and SDS_MISC concurrently with the PCS and MAC link_up paths and pcs_get_state(), so those accesses are serialized by a new sds_lock. The work is cancelled in teardown(), and in pcs_config() before SDS_MISC is touched, since a link that flaps would otherwise re-arm the sequence against a half-reconfigured SerDes. Co-developed-by: Oleg Gavrilov Signed-off-by: Oleg Gavrilov Signed-off-by: Mieczyslaw Nalewaj --- drivers/net/dsa/realtek/rtl8365mb_main.c | 231 +++++++++++++++++++++-- 1 file changed, 216 insertions(+), 15 deletions(-) diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/realtek/rtl8365mb_main.c index aad26ba..a322c42 100644 --- a/drivers/net/dsa/realtek/rtl8365mb_main.c +++ b/drivers/net/dsa/realtek/rtl8365mb_main.c @@ -104,6 +104,7 @@ #include #include #include +#include #include "realtek.h" #include "realtek-smi.h" @@ -300,6 +301,23 @@ #define RTL8365MB_SDS_MISC_SGMII_SPD_MASK GENMASK(8, 7) #define RTL8365MB_SDS_MISC_MAC8_SEL_SGMII_MASK BIT(6) +/* Re-latch retry interval and attempt budget. Each attempt parks the + * SerDes for 20 ms, so a far end that never comes up must not be retried + * at this rate forever, and the interval must not be so tight that + * back-to-back parks starve a link that is about to latch. The count is + * reset to 1 by pcs_config() and to 0 whenever the receiver latches; + * attempts start at pcs_config(), well before the far end MAC is up, so + * with the interval below the budget is roughly RELATCH_MAX_TRIES seconds, + * generous enough to outlast a slow conduit. + */ +#define RTL8365MB_D_SDS_RELATCH_INTERVAL (HZ) +#define RTL8365MB_D_SDS_RELATCH_MAX_TRIES 15 + +/* How often a latched (or out-of-budget) SerDes is checked, and re-latched + * if still down. Much slower than the re-latch interval. + */ +#define RTL8365MB_D_SDS_HEALTHCHECK_INTERVAL (10 * HZ) + /* SerDes internal registers, accessed via the SDS_INDACS registers. The BMCR * data path reset holds BMCR_ANENABLE | BMCR_ISOLATE while toggling the * vendor-specific low bits from phase 1 to phase 2, which triggers a data path @@ -950,9 +968,17 @@ struct rtl8365mb { const struct rtl8365mb_chip_info *chip_info; struct rtl8365mb_cpu cpu; struct mutex mib_lock; + /* Serializes access to the shared SDS_INDACS ADR/CMD/DATA window and + * to RTL8365MB_SDS_MISC_REG, reachable both from phylink's PCS poll + * (mb->pcs.poll) and from the family D SerDes re-latch work. + */ + struct mutex sds_lock; struct rtl8365mb_port ports[RTL8365MB_MAX_NUM_PORTS]; struct phylink_pcs pcs; bool sds_supported; + struct delayed_work sds_relatch; /* re-latch edges and link health check */ + unsigned int sds_relatch_count; /* next attempt of the episode, 0 once latched */ + u32 sds_misc_target_val; }; #define pcs_to_rtl8365mb(_pcs) container_of((_pcs), struct rtl8365mb, pcs) @@ -1356,43 +1382,53 @@ static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, static int rtl8365mb_sds_write(struct realtek_priv *priv, u8 index, u16 addr, u16 data) { + struct rtl8365mb *mb = priv->chip_data; int ret; + mutex_lock(&mb->sds_lock); + ret = regmap_write(priv->map, RTL8365MB_SDS_INDACS_DATA_REG, data); if (ret) - return ret; + goto out_unlock; ret = regmap_write(priv->map, RTL8365MB_SDS_INDACS_ADR_REG, addr); if (ret) - return ret; + goto out_unlock; /* The SerDes indirect access engine completes the command within the * register write transaction, so there is no need to wait or poll for * completion before the next access, matching the vendor driver. */ - return regmap_write(priv->map, RTL8365MB_SDS_INDACS_CMD_REG, - RTL8365MB_SDS_INDACS_CMD_RUN_MASK | - RTL8365MB_SDS_INDACS_CMD_WR_MASK | - FIELD_PREP(RTL8365MB_SDS_INDACS_CMD_INDEX_MASK, - index)); + ret = regmap_write(priv->map, RTL8365MB_SDS_INDACS_CMD_REG, + RTL8365MB_SDS_INDACS_CMD_RUN_MASK | + RTL8365MB_SDS_INDACS_CMD_WR_MASK | + FIELD_PREP(RTL8365MB_SDS_INDACS_CMD_INDEX_MASK, + index)); + +out_unlock: + mutex_unlock(&mb->sds_lock); + return ret; } static int rtl8365mb_sds_read(struct realtek_priv *priv, u8 index, u16 addr, u16 *data) { + struct rtl8365mb *mb = priv->chip_data; u32 val; int ret; + mutex_lock(&mb->sds_lock); + ret = regmap_write(priv->map, RTL8365MB_SDS_INDACS_ADR_REG, addr); if (ret) - return ret; + goto out_unlock; ret = regmap_write(priv->map, RTL8365MB_SDS_INDACS_CMD_REG, RTL8365MB_SDS_INDACS_CMD_RUN_MASK | FIELD_PREP(RTL8365MB_SDS_INDACS_CMD_INDEX_MASK, index)); if (ret) - return ret; + goto out_unlock; /* Wait for the indirect read to complete: the engine clears the BUSY * bit once the data register holds the result. @@ -1402,15 +1438,19 @@ static int rtl8365mb_sds_read(struct realtek_priv *priv, u8 index, !(val & RTL8365MB_SDS_INDACS_CMD_BUSY_MASK), 10, 1000); if (ret) - return ret; + goto out_unlock; ret = regmap_read(priv->map, RTL8365MB_SDS_INDACS_DATA_REG, &val); if (ret) - return ret; + goto out_unlock; *data = val; - return 0; + ret = 0; + +out_unlock: + mutex_unlock(&mb->sds_lock); + return ret; } /* The vendor driver selects between two sets of SerDes tuning parameters based @@ -1532,6 +1572,13 @@ static int rtl8365mb_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, is_d = rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D; + /* Cancel any in-flight re-latch edge before touching SDS_MISC: the + * work drops sds_lock across its sleep and could otherwise interleave + * with the reconfiguration below. + */ + if (is_d) + cancel_delayed_work_sync(&mb->sds_relatch); + /* Select the appropriate tuning table and SDS mode */ if (interface == PHY_INTERFACE_MODE_2500BASEX) { if (is_d) { @@ -1612,12 +1659,16 @@ static int rtl8365mb_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, RTL8365MB_SDS_MISC_MAC8_SEL_HSGMII_MASK; } + mutex_lock(&mb->sds_lock); ret = regmap_update_bits(priv->map, RTL8365MB_SDS_MISC_REG, misc_mask, misc_val); + mutex_unlock(&mb->sds_lock); if (ret) return ret; - if (!is_d) { + if (is_d) { + WRITE_ONCE(mb->sds_misc_target_val, misc_val); + } else { val = sds_mode << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(id); ret = regmap_update_bits(priv->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(id), @@ -1664,8 +1715,140 @@ static int rtl8365mb_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, val &= ~RTL8365MB_SDS_NWAY_EN_MASK; val |= RTL8365MB_SDS_NWAY_RESTART_MASK; - return rtl8365mb_sds_write(priv, sds_index, - RTL8365MB_SDS_REG_NWAY, val); + ret = rtl8365mb_sds_write(priv, sds_index, + RTL8365MB_SDS_REG_NWAY, val); + if (ret) + return ret; + + if (is_d) { + /* Start a new re-latch episode and kick off the first attempt; + * see rtl8365mb_sds_relatch_work() for why this cannot wait + * for phylink to ask again. + */ + WRITE_ONCE(mb->sds_relatch_count, 1); + schedule_delayed_work(&mb->sds_relatch, 0); + } + + return 0; +} + +/* The family D receiver latches on a DISABLE -> mode edge in SDS_MISC + * rather than on the value, and only once the far-end MAC has brought up + * its half of the link. No local signal predicts that (bit 8 of the SDS + * link-status word does not change ahead of it), so the work cannot wait + * for it, only check afterwards whether an edge took. Nor does phylink + * ever call rtl8365mb_pcs_get_state() for this fixed-link port + * (mb->pcs.poll only arms phylink's own poll for in-band links), so this + * cannot rely on being polled at all. Instead, pcs_config() starts an + * episode and this work re-arms itself after every edge, its next run + * checking whether the edge took. + * + * An episode is capped at RTL8365MB_D_SDS_RELATCH_MAX_TRIES edges, spaced + * RTL8365MB_D_SDS_RELATCH_INTERVAL apart, so that a far end which never + * comes up costs a bounded burst of 20 ms parks. The run after the last + * edge only checks whether it took and reports failure; from then on one + * edge is driven per RTL8365MB_D_SDS_HEALTHCHECK_INTERVAL, so a far end + * that comes up late is recovered without a reconfiguration. Once the + * receiver has latched the work just polls the link at the same slow + * interval; finding it down then starts a new episode, e.g. after the far + * end reset its PLL without a reconfiguration. + * + * sds_relatch_count is the number of the next attempt of the episode: 0 + * while latched, 1..MAX_TRIES in budget, MAX_TRIES + 1 for the run that + * only reports, and above that once out of budget. + */ +static void rtl8365mb_sds_relatch_work(struct work_struct *work) +{ + struct rtl8365mb *mb = container_of(to_delayed_work(work), + struct rtl8365mb, sds_relatch); + struct realtek_priv *priv = mb->priv; + u32 park = (READ_ONCE(mb->sds_misc_target_val) & + ~RTL8365MB_D_SDS_MISC_MODE_FIELD_MASK) | + RTL8365MB_D_PORT_SDS_MODE_DISABLE; + unsigned long delay = RTL8365MB_D_SDS_RELATCH_INTERVAL; + unsigned int attempts; + u16 status; + int ret; + + /* The condition that queued this work may already be stale by the + * time it runs (e.g. an earlier edge from a prior attempt just + * latched). Parking an already-live link would drop it for no + * reason. + */ + ret = rtl8365mb_sds_read(priv, RTL8365MB_D_SDS_EXT0_INDEX, + RTL8365MB_SDS_REG_LINK_STATUS, &status); + if (ret) { + dev_err_ratelimited(priv->dev, + "failed to read SerDes link status: %pe\n", + ERR_PTR(ret)); + goto rearm; + } + if (status & RTL8365MB_SDS_LINK_STATUS_LINK_MASK) { + /* Latched: end the episode, keep watching for a later loss. */ + WRITE_ONCE(mb->sds_relatch_count, 0); + delay = RTL8365MB_D_SDS_HEALTHCHECK_INTERVAL; + goto rearm; + } + + attempts = READ_ONCE(mb->sds_relatch_count); + if (!attempts) { + dev_warn(priv->dev, + "SerDes link lost outside a reconfiguration; re-latching\n"); + attempts = 1; + } else if (attempts == RTL8365MB_D_SDS_RELATCH_MAX_TRIES + 1) { + /* This run only checked whether the last in-budget edge + * took. The first out-of-budget edge comes one healthcheck + * interval from now, not on this pass. + */ + WRITE_ONCE(mb->sds_relatch_count, attempts + 1); + dev_warn(priv->dev, + "SerDes did not latch after %u re-latch attempts; still retrying every %d s\n", + RTL8365MB_D_SDS_RELATCH_MAX_TRIES, + RTL8365MB_D_SDS_HEALTHCHECK_INTERVAL / HZ); + delay = RTL8365MB_D_SDS_HEALTHCHECK_INTERVAL; + goto rearm; + } + + if (attempts <= RTL8365MB_D_SDS_RELATCH_MAX_TRIES) + WRITE_ONCE(mb->sds_relatch_count, attempts + 1); + else + /* Past the fast-retry budget. The receiver latches only on a + * DISABLE -> mode edge and nothing re-runs pcs_config() for a + * fixed-link port, so keep driving one edge per interval. + */ + delay = RTL8365MB_D_SDS_HEALTHCHECK_INTERVAL; + + mutex_lock(&mb->sds_lock); + ret = regmap_update_bits(priv->map, RTL8365MB_SDS_MISC_REG, + RTL8365MB_D_SDS_MISC_CFG_MASK, park); + mutex_unlock(&mb->sds_lock); + if (ret) { + dev_err_ratelimited(priv->dev, + "failed to park SDS_MISC: %pe\n", + ERR_PTR(ret)); + goto rearm; + } + + usleep_range(20000, 21000); + + mutex_lock(&mb->sds_lock); + ret = regmap_update_bits(priv->map, RTL8365MB_SDS_MISC_REG, + RTL8365MB_D_SDS_MISC_CFG_MASK, + READ_ONCE(mb->sds_misc_target_val)); + mutex_unlock(&mb->sds_lock); + if (ret) { + dev_err_ratelimited(priv->dev, + "failed to restore SDS_MISC: %pe\n", + ERR_PTR(ret)); + goto rearm; + } + + dev_dbg(priv->dev, "SerDes re-latch edge driven (attempt %u)\n", + attempts); + + /* This edge may not have taken either; the next run checks. */ +rearm: + schedule_delayed_work(&mb->sds_relatch, delay); } static bool rtl8365mb_interface_is_serdes(phy_interface_t interface) @@ -1730,7 +1913,9 @@ static void rtl8365mb_pcs_get_state(struct phylink_pcs *pcs, /* The speed and duplex are forced; read them back from the values * programmed into the SerDes MISC register. */ + mutex_lock(&mb->sds_lock); ret = regmap_read(priv->map, RTL8365MB_SDS_MISC_REG, &val); + mutex_unlock(&mb->sds_lock); if (ret) { state->link = false; return; @@ -1800,7 +1985,9 @@ static void rtl8365mb_pcs_link_up(struct phylink_pcs *pcs, * force from rtl8365mb_phylink_mac_link_up(), where the resolved pause * modes are known. */ + mutex_lock(&mb->sds_lock); ret = regmap_update_bits(priv->map, RTL8365MB_SDS_MISC_REG, mask, val); + mutex_unlock(&mb->sds_lock); if (ret) { dev_err(priv->dev, "failed to force SerDes link: %pe\n", ERR_PTR(ret)); @@ -2108,11 +2295,13 @@ static void rtl8365mb_phylink_mac_link_up(struct phylink_config *config, if (rx_pause) val |= RTL8365MB_SDS_MISC_SGMII_RXFC_MASK; + mutex_lock(&mb->sds_lock); ret = regmap_update_bits(priv->map, RTL8365MB_SDS_MISC_REG, RTL8365MB_SDS_MISC_SGMII_TXFC_MASK | RTL8365MB_SDS_MISC_SGMII_RXFC_MASK, val); + mutex_unlock(&mb->sds_lock); if (ret) dev_err(priv->dev, "failed to force SerDes pause modes on port %d: %pe\n", @@ -3324,6 +3513,10 @@ static int rtl8365mb_setup(struct dsa_switch *ds) */ mb->pcs.poll = true; + if (rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D) + INIT_DELAYED_WORK(&mb->sds_relatch, + rtl8365mb_sds_relatch_work); + ret = rtl8365mb_reset_chip(priv); if (ret) { dev_err(priv->dev, "failed to reset chip: %pe\n", @@ -3508,6 +3701,10 @@ out_error: static void rtl8365mb_teardown(struct dsa_switch *ds) { struct realtek_priv *priv = ds->priv; + struct rtl8365mb *mb = priv->chip_data; + + if (rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D) + cancel_delayed_work_sync(&mb->sds_relatch); rtl8365mb_stats_teardown(priv); rtl8365mb_irq_teardown(priv); @@ -3578,6 +3775,10 @@ static int rtl8365mb_detect(struct realtek_priv *priv) else priv->num_ports = RTL8365MB_MAX_NUM_PORTS; + ret = devm_mutex_init(priv->dev, &mb->sds_lock); + if (ret) + return ret; + mb->priv = priv; mb->cpu.trap_port = RTL8365MB_MAX_NUM_PORTS; mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL; -- 2.53.0